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Scholar
Scholar
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Registered: ‎06-10-2008

AXI4-Stream FIFO TDFD AXI4 address space

Hi,

 

For the AXI4-Stream FIFO when used with a full AXI4 data interface, is the TDFD address fully decoded or will it mirror at multiple addresses? I'm asking because it is rather inefficient to have to send the data through a keyhole instead of to a block of memory for a processor like the ARM core in a Zynq (or a cache flush on any other system).

 

PG080 says that TDFD is at C_AXI4_BASEADDR + 0x0000 and RDFD is at C_AXI4_BASEADDR + 0x1000. Does that mean that every write to any 4-fold (32bit) or 8-fold address (64bit) in between is good enough to get the data across? In other words: Can I use the ARM LDM/STM instructions to transfer blocks of data?

 

Maarten

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Scholar
Scholar
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Registered: ‎06-10-2008

Ok, since nobody answered, I just tried to find out its behavior. I gave the FIFO a full AXI4 data interface and that still works ok when I just write one word at a time. But when I use memcpy to write multiple words, my Linux crashes and reboots! So what was the point of moving TDFD and RDFD in the 4.1 release?

 

Can someone from Xilinx please reply?

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Scholar
Scholar
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Registered: ‎06-10-2008

It seems to me that this thing violates the AXI standard. According to the address map it claims a block of 64kB. But a simple test with a write of a word to 0x43C10004 using devmem makes it lock up. I think it should return a bus error instead if it is not allowed to write to this address. But much better is just to accept words on every address.

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