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Registered: ‎07-11-2011

AXI4 Streams, DMA and EDK 13.2

The short term objective of my design is to move ADC samples into DRAM as efficiently as possible and interrupt the Microblaze CPU when a block of conversions is done.  To that end, I created a system in XPS that has some of my own IP (really, just the stub created by the "Create or Import Peripheral..." wizard) to take the ADC conversions and put them into an AXI4 stream, then I hooked that up to the "AXI DMA Engine 4.00a".  IIUC, that takes the data from an AXI4 Stream and puts them on the AXI4 bus.  From there, they are passed into a write-only port on the MCB memory controller.  CPU interrupts will be handled by the DMA engine.


So far, so good.  But in the mid-term future we will want to reverse the process (move samples from memory through the DMA controller and out via my IP to a DAC).  For the life of me, I cannot get XPS to make a connection between the S_AXIS in my IP and the M_AXIS_MM2S on the DMA engine (see attached screenshot).  It behaves as if the DMA engine can even recognize the S_AXIS bus as being a compatible AXI4 stream.


The bothersome thing is that my IP is (for now) just the output for the "Create or Import Peripheral..." wizard, where I chose AXI Stream as my bus protocol.


Can anyone lend me a clue?


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6 Replies
Registered: ‎07-14-2011

I have the same doubt.


I need map in memory a AXI Stream peripheral using the DMA channel.



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Xilinx Employee
Xilinx Employee
Registered: ‎01-18-2008

The axi_dma is really an ethernet DMA as it stands right now. I'd recommend that you construct a simple system using BSB that has temac + DMA. Then see how the connections are, and try to make similar connections.


If XPS doesn't allow you to make those connections, then I'd check the MPD files of ethernet and compare it with your custom pcore to see the differences in how the streaming interfaces are defined.

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Registered: ‎06-23-2010

I'm also trying to figure out how to interface an AXI stream to external fpga logic.  When I add the AXI DMA Engine IP, the S_AXIS_S2MM does not show up in the port definitions of the System Assembly View (screenshot attached).  The AXI stream interface seems easy enough, but it is not at all clear how to use the tools to interface it with external fpga logic.  What I am trying to do is simply use the DMA Engine portion of the IP to send input data directly to memory and interrupt the processor when complete.  How exactly do I create a stream input connection for data coming from somewhere else in the fpga (external to the microblaze)?


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Registered: ‎12-16-2011

  I found that if you change the protocol to XIL_AXI_STREAM_ETH_DATA in your IP mpd file you can get it connected to the AXI_DMA, but I've not tested it yet. 

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Registered: ‎01-14-2012

I did have the same problem with 13.3, but since I am using the AXI DMA for both Ethernet and a proprietary interface (two instances of AXI DMA 5.00), I had to invent my own "protocol" name for the second instance of AXI DMA and my proprietary IP. Unfortunately, the protocol parameter is given the property "ASSIGNMENT = CONSTANT" in the MPD file, so it can't be changed by setting it in the MHS file. I made the AXI DMA a "local IP" and changed the protocol name. 


I have asked Xilinx to change the MPD file so that the protocol parameter is given a different assignment property



Once I had changed the protocol name, the connections in XPS worked as they should.


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Registered: ‎12-15-2011

Hello ....
At the moment I'm doing my diplom project at higher technical college. I have quite the same troubles. From a camera data is read in which get into my selfmade IP Core. The core transfers data to the DMA and finally they get directly into the DDR3-RAM (so far the theoretical part).
There are no examples given, so I have problems with the configuration of the DMA to communicate with the IP Core. Status and Control-Streams are turned off @ DMA.
Are there any further necessarry configurations? Do I have to change the code in the MPD-File (AXI-Stream-Protocol = XIL_AXI_STREAM_ETH_DATA)?

Referring to my IP Core: Are TKEEP and TLAST essential or are there other alternatives to mark the end of a packet?
Maybe you know an example project for our problems to compare, because there are no examples provided. That would help a lot!
Otherwise, would you mind exchanging e-mail addresses, so we could dicuss in detail?

Thank you in advance!

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