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AXI4lite and Instruction Cache

Visitor
Posts: 1
Registered: ‎09-25-2013

AXI4lite and Instruction Cache

Hello everyone,

 

I have designed an AXI4LITE SDRAM controller, and i work on a spartan6 FPGA. I plan to store  my Microblaze application on SDRAM, and execute it from SDRAM. To make this possible, i have seen in some example projects that instruction cache have to be enabled. My controller is not capable of burst read/write since it is connected to MB through AXI4LITE. When enabling instruction caches, there is a setting called Line length, and it can be set to either 4 or 8, and it means 4 or 8 word access. Is it not possible to use instruction caches to access an external memory using AXI4LITE?

Posts: 641
Registered: ‎07-31-2012

Re: AXI4lite and Instruction Cache

Hi,

 

The caches works like the below:

1. The cache is implemented by BRAM within MicroBlaze. It won't use any external memory.

2. The cache will only be used when MicroBlaze access an address within cacheable memory address space.

3. If the applicaion runs out of BRAM, I-side cache won't be used since the BRAM is not cached and can't be cached.

4. There's no D-side cache (I don't even think it's valid to set the dache size to '0' when it's enabled.), so you won't see any performance improvements when read/write SDRAM

 

Regards

Praveen

Xilinx Employee
Posts: 977
Registered: ‎08-06-2007

Re: AXI4lite and Instruction Cache

Hi,

 

MicroBlaze caches are using burst accesses to read and write instruction/data and will thus not work with AXI4Lite.

If the caches are turned off, they would not do burst requests but what use would the cache do if always turned off?

 

Göran