02-14-2017 12:31 PM
I have designed an AXI4LITE SDRAM controller, and i work on a spartan6 FPGA. I plan to store my Microblaze application on SDRAM, and execute it from SDRAM. To make this possible, i have seen in some example projects that instruction cache have to be enabled. My controller is not capable of burst read/write since it is connected to MB through AXI4LITE. When enabling instruction caches, there is a setting called Line length, and it can be set to either 4 or 8, and it means 4 or 8 word access. Is it not possible to use instruction caches to access an external memory using AXI4LITE?
03-19-2017 08:13 AM
The caches works like the below:
1. The cache is implemented by BRAM within MicroBlaze. It won't use any external memory.
2. The cache will only be used when MicroBlaze access an address within cacheable memory address space.
3. If the applicaion runs out of BRAM, I-side cache won't be used since the BRAM is not cached and can't be cached.
4. There's no D-side cache (I don't even think it's valid to set the dache size to '0' when it's enabled.), so you won't see any performance improvements when read/write SDRAM