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Observer
Observer
7,362 Views
Registered: ‎04-03-2008

Adding IPs generates suspicious errors

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Hi.

 

I had a fully working design with an embedded processor implemented as a top module in ISE (and the UCF-file attached to the top module).

 

I wanted to add an XGpio IP, and an UartLite IP to the design. I added these IPs in EDK, attached them to the PLB bus, made the external port connections, and assigned addresses. 

For some reason EDK 9.2i is not creating the new constrains in the UCF file upon making a port external (maybe this is because I'm working on a custom board). To work around this, I find the related pin name in the top of the mhs-file, and adds it to the end of the UCFfile. 

 

I then go back to ISE, and run the "Generate Programming File"-process. ISE fails during the "Implement Design" process. It gives the following error for every single contrain in the UCF file:

 

ERROR:NgdBuild:755 - "ucf-file-pathname"

   Line 7: Could not find net(s) 'sys_clk_pin' in the design.  To suppress this

   error specify the correct net name or remove the constraint.  The 'Allow

   Unmatched LOC Constraints' ISE property can also be set ( -aul switch for

   command line users). 

 

 Anybody knows some way to work around this?

 

Best regards

Kasper 

 

 PS: I'v added the UCF files

Message Edited by lhadrepsak on 08-31-2009 12:41 AM
Message Edited by lhadrepsak on 08-31-2009 12:44 AM
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Observer
Observer
5,641 Views
Registered: ‎04-03-2008

Re: Adding IPs generates suspicious errors

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I've solved the issue.

 

The instance name cannot start with a number. Must start with a letter.

 

A "thank you" to everybody for their effort.

 

//Kasper 

Message Edited by lhadrepsak on 08-31-2009 06:19 AM

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Contributor
Contributor
7,351 Views
Registered: ‎07-22-2009

Re: Adding IPs generates suspicious errors

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Hi, try to delete one of the two "Net sys_clk_pin TNM_Net = sys_clc_pin":

 

 Net "sys_clk_pin"  LOC = "p80" | IOSTANDARD = LVTTL;
Net sys_clk_pin TNM_NET = sys_clk_pin;
## System level constraints
Net sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 25000 ps;

 

 I don't know if it is that, but it's useless to write tthis line twice.

 

Moreover, check if the pin p80 really exists in your FPGA, and, why not, try to write P80 instead of p80...But if it is that, it's strange...

 

Best Regards,

 

Fabien

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Observer
Observer
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Registered: ‎04-03-2008

Re: Adding IPs generates suspicious errors

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Hi Fabien.

 

Thanks for your reply.

 

There's obviously no need to write the sys_clk_pin-line twice - nice spotted :)

 

But unfortunately it didn't solve my issue...

 

I've attached the MHS-file to this post. 

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Contributor
Contributor
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Registered: ‎07-22-2009

Re: Adding IPs generates suspicious errors

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Hi,

 

Try to write in your UCF "sys_clk_s_pin" instead of "sys_clk_pin".

 

Best Regards,

 

Fabien

 

Message Edited by fabiend on 08-31-2009 01:57 AM
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Explorer
Explorer
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Registered: ‎05-15-2009

Re: Adding IPs generates suspicious errors

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After you add the custom cores and assigned the ports do Rescan User Repositories. Make sure sys_clk_pin is made external in XPS within the system assembly view->ports. Then go to the data folder of your XPS project and import the *.ucf from that file to the top level in ISE. Remove the previous one you had and add some ports you manually placed in the original. I am also a bit bored about the | iostandart and the location between "", why not

 

Net sys_clk_pin LOC=p80;
Net sys_clk_pin IOSTANDARD = LVTTL;

 

?

 

Best,

JM

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Observer
Observer
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Registered: ‎04-03-2008

Re: Adding IPs generates suspicious errors

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changing to sys_clk_s_pin didn't help - could you breifly explain what you wanted to accomplish with that?

 

//Kasper 

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Explorer
Explorer
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Registered: ‎05-15-2009

Re: Adding IPs generates suspicious errors

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The system clock net must be the same from the top level (ISE) to your microblaze (XPS) architecture project. This is, the clock signal that feeds the clock generator (if you have it) on XPS must be visible at the top level, and connected to the sys_clk_pin which in turn is connected to the correct OSC pin. As I said, XPS creates a user constraints file ready for you to use in the top level, at least when you use a development board (I'm not sure if it does the same for a custom board). Search on the data folder of your project. This is just to make sure the net and its location are correctly mapped.

 

Anyway, have you tried to suppress the "" from the LOC= ?

 

Best,

JM

Message Edited by jmonteiro-dme on 08-31-2009 03:26 AM
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Observer
Observer
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Registered: ‎04-03-2008

Re: Adding IPs generates suspicious errors

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Hi JM.

 

I'm running the Generate Programming File now.

 

I've made the changes to the UCF file, and attached it to this post.

 

I've followed your post in the order given below:

 

1: Removed the UCF file in ISE

 

2: Cleaned project files in ISE 

 

3: Made the changes you requested in the UCF file

 

4: Made sure, that the clk port is externally connected 

 

5: Rescaned user repositories

 

5: Added the UCF file in ISE again. Imported it from the data folder. 

 

6: Ran "Generate Programming File"

 

The process is currently running. Will post result once done

 

//Kasper 

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Observer
Observer
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Registered: ‎04-03-2008

Re: Adding IPs generates suspicious errors

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Okay, the process has finished, but with the exact same errors as before.

 

At first it generated some "new" errors, but that's because I had forgotten three semicolons - once I fixed that, the old errors was back. :smileymad:  

 

//Kasper 

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Explorer
Explorer
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Registered: ‎05-15-2009

Re: Adding IPs generates suspicious errors

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Given that, i suspect the error must be on the location you assign for that net. What FPGA are you using? are you sure that p80 is the OSC pin of your FPGA? Have you seen the datasheet?
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Observer
Observer
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Registered: ‎04-03-2008

Re: Adding IPs generates suspicious errors

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Hi JM.

 

I've used the p80 as clock pin in serveral designs before, and it worked perfectly in this specific design before adding the last UartLite IP, and the 2-bit wide GPIO.

 

But just for the record, I'm running on a Spartan 3E 500k gates PQ208 pin package. 

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Explorer
Explorer
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Registered: ‎05-15-2009

Re: Adding IPs generates suspicious errors

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Are the cores correctly clocked? By default, the system clock from the top level is connected to the XPS clock generator, which then clocks all the cores in the uB architecture. the cores should connect to the clock provided by the clock generator, i.e., sys_clk_s (if you use it), not to the system clock sys_clk_pin, which should be by default connected to the dcm_clk..
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Observer
Observer
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Registered: ‎04-03-2008

Re: Adding IPs generates suspicious errors

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I've solved the issue.

 

The instance name cannot start with a number. Must start with a letter.

 

A "thank you" to everybody for their effort.

 

//Kasper 

Message Edited by lhadrepsak on 08-31-2009 06:19 AM

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