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6,464 Views
Registered: ‎04-20-2011

Associating DMA_REQ and DMA_ACK with clock pin

Hi

 

First of all, extremely dissapointed that XIlinx stopped allowing to open web cases. 

 

But, here goes:

 

I'm trying to build a simple design for a Zynq 7045 using Vivado and IP integrator. Please see below a tcl script with the system I'm trying to build. When I try to validate the system I get warnings such as:

 

 

[BD 41-967] AXI interface pin /processing_system7_1/DMA0_REQ is not associated to any clock pin. It may not work correctly.

 

This message repeats for both DMA_REQ and both DMA_ACK pins. I cannot see anywhere in IP integrator where I can assign a clock pin to the DMA_REQ and DMA_ACK pins of the processing system (as you can see from the design I have assigned clock pins to the DMA_REQ and DMA_ACK external pins, so I assume this isn't the problem).

 

Seeing that this is a critical warning and not an error, is it safe to ignore ? If not, how can I fix the problem ?

 

Thanks

 

Nir

 

The tcl script (the forum will not let me attach it)

 

# This is a generated script based on design: design_1
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
#
# To test this script, run the following commands from Vivado Tcl console:
# source design_1_script.tcl

# If you do not already have a project created,
# you can create a project using the following command:
#    create_project project_1 myproj -part xc7vx485tffg1157-1 -force

# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
#    create_bd_design design_1

# Creating design if needed
if { [get_files *.bd] eq "" } {
   puts "INFO: Currently there are no designs in project, so creating one..."
   create_bd_design design_1
}



# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {

  if { $parentCell eq "" } {
     set parentCell [get_bd_cells /]
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     puts "ERROR: Unable to find parent cell <$parentCell>!"
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj


  # Create interface ports
  set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
  set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
  set M00_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M00_AXI ]
  set_property -dict [ list CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} CONFIG.ADDR_WIDTH {32}  ] $M00_AXI
  set M01_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M01_AXI ]
  set_property -dict [ list CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} CONFIG.ADDR_WIDTH {32}  ] $M01_AXI
  set DMA0_ACK [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 DMA0_ACK ]
  set DMA1_ACK [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 DMA1_ACK ]
  set DMA0_REQ [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 DMA0_REQ ]
  set_property -dict [ list CONFIG.TDATA_NUM_BYTES {0} CONFIG.TDEST_WIDTH {0} CONFIG.TID_WIDTH {0} CONFIG.TUSER_WIDTH {2} CONFIG.HAS_TREADY {1} CONFIG.HAS_TSTRB {0} CONFIG.HAS_TKEEP {0} CONFIG.HAS_TLAST {1} CONFIG.PHASE {0.000} CONFIG.LAYERED_METADATA {undef}  ] $DMA0_REQ
  set DMA1_REQ [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 DMA1_REQ ]
  set_property -dict [ list CONFIG.TDATA_NUM_BYTES {0} CONFIG.TDEST_WIDTH {0} CONFIG.TID_WIDTH {0} CONFIG.TUSER_WIDTH {2} CONFIG.HAS_TREADY {1} CONFIG.HAS_TSTRB {0} CONFIG.HAS_TKEEP {0} CONFIG.HAS_TLAST {1} CONFIG.PHASE {0.000} CONFIG.LAYERED_METADATA {undef}  ] $DMA1_REQ

  # Create ports
  set fclk [ create_bd_port -dir O -type clk fclk ]
  set_property -dict [ list CONFIG.ASSOCIATED_BUSIF {M00_AXI:M01_AXI:DMA0_REQ:DMA1_REQ:DMA0_ACK:DMA1_ACK}  ] $fclk

  # Create instance: processing_system7_1, and set properties
  set processing_system7_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.2 processing_system7_1 ]
  set_property -dict [ list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {100} CONFIG.PCW_USE_DMA0 {1} CONFIG.PCW_USE_DMA1 {1} CONFIG.PCW_EN_CLK1_PORT {0} CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {0} CONFIG.PCW_SD0_PERIPHERAL_ENABLE {0} CONFIG.PCW_UART1_PERIPHERAL_ENABLE {0} CONFIG.PCW_WDT_PERIPHERAL_ENABLE {0} CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0} CONFIG.PCW_USB0_PERIPHERAL_ENABLE {0} CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {0} CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {0}  ] $processing_system7_1

  # Create instance: axi_mem_intercon, and set properties
  set axi_mem_intercon [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.0 axi_mem_intercon ]
  set_property -dict [ list CONFIG.NUM_MI {2}  ] $axi_mem_intercon

  # Create instance: proc_sys_reset, and set properties
  set proc_sys_reset [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset ]

  # Create interface connections
  connect_bd_intf_net -intf_net processing_system7_1_m_axi_gp0 [get_bd_intf_pins processing_system7_1/M_AXI_GP0] [get_bd_intf_pins axi_mem_intercon/S00_AXI]
  connect_bd_intf_net -intf_net processing_system7_1_ddr [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_1/DDR]
  connect_bd_intf_net -intf_net processing_system7_1_fixed_io [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_1/FIXED_IO]
  connect_bd_intf_net -intf_net axi_mem_intercon_m00_axi [get_bd_intf_ports M00_AXI] [get_bd_intf_pins axi_mem_intercon/M00_AXI]
  connect_bd_intf_net -intf_net axi_mem_intercon_m01_axi [get_bd_intf_ports M01_AXI] [get_bd_intf_pins axi_mem_intercon/M01_AXI]
  connect_bd_intf_net -intf_net processing_system7_1_dma0_ack [get_bd_intf_ports DMA0_ACK] [get_bd_intf_pins processing_system7_1/DMA0_ACK]
  connect_bd_intf_net -intf_net processing_system7_1_dma1_ack [get_bd_intf_ports DMA1_ACK] [get_bd_intf_pins processing_system7_1/DMA1_ACK]
  connect_bd_intf_net -intf_net dma0_req_1 [get_bd_intf_ports DMA0_REQ] [get_bd_intf_pins processing_system7_1/DMA0_REQ]
  connect_bd_intf_net -intf_net dma1_req_1 [get_bd_intf_ports DMA1_REQ] [get_bd_intf_pins processing_system7_1/DMA1_REQ]

  # Create port connections
  connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins processing_system7_1/FCLK_RESET0_N] [get_bd_pins proc_sys_reset/ext_reset_in]
  connect_bd_net -net proc_sys_reset_peripheral_aresetn [get_bd_pins proc_sys_reset/peripheral_aresetn] [get_bd_pins axi_mem_intercon/S00_ARESETN] [get_bd_pins axi_mem_intercon/M00_ARESETN] [get_bd_pins axi_mem_intercon/M01_ARESETN]
  connect_bd_net -net proc_sys_reset_interconnect_aresetn [get_bd_pins proc_sys_reset/interconnect_aresetn] [get_bd_pins axi_mem_intercon/ARESETN]
  connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_ports fclk] [get_bd_pins processing_system7_1/FCLK_CLK0] [get_bd_pins processing_system7_1/M_AXI_GP0_ACLK] [get_bd_pins axi_mem_intercon/ACLK] [get_bd_pins axi_mem_intercon/S00_ACLK] [get_bd_pins axi_mem_intercon/M00_ACLK] [get_bd_pins axi_mem_intercon/M01_ACLK] [get_bd_pins proc_sys_reset/slowest_sync_clk] [get_bd_pins processing_system7_1/DMA0_ACLK] [get_bd_pins processing_system7_1/DMA1_ACLK]

  # Create address segments
  create_bd_addr_seg -range 0x10000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs M00_AXI/Reg] SEG1
  create_bd_addr_seg -range 0x10000 -offset 0x43C10000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs M01_AXI/Reg] SEG2
  

  # Restore current instance
  current_bd_instance $oldCurInst
}


#####################################################
# Main Flow
#####################################################

create_root_design ""

 

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8 Replies
Xilinx Employee
Xilinx Employee
6,449 Views
Registered: ‎07-30-2007

Re: Associating DMA_REQ and DMA_ACK with clock pin

I've not looked at your TCL, but I'd guess that this will answer your question.

http://www.xilinx.com/support/answers/56609.htm

 

Basically, every AXI interface needs to manually have a clock associated to it, so that other IP like AXI Interconnect can perform DRCs and additional features like automatic clock conversion.

 

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6,434 Views
Registered: ‎04-20-2011

Re: Associating DMA_REQ and DMA_ACK with clock pin

Hi Dylan

 

Thanks, but the AR you've pointed to was where I started. I've done everything it suggested and these warning still come up. It's unclear what can  be done to make them go away and if they are actually a cause for concern. If you could run the script you'd see this.

 

Nir

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Scholar stephenm
Scholar
6,421 Views
Registered: ‎05-06-2012

Re: Associating DMA_REQ and DMA_ACK with clock pin

There is a pin property called associated_busif that is blank due to the fact that you are making this external. this would normally be used to determine what clock domain is to be used.  however, you have you clocks connected so you can ignore this.

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6,416 Views
Registered: ‎04-20-2011

Re: Associating DMA_REQ and DMA_ACK with clock pin

Hi Stephenm

 

Thanks for replying. Are you referring to the following line?

set_property -dict [ list CONFIG.ASSOCIATED_BUSIF {M00_AXI:M01_AXI:DMA0_REQ:DMA1_REQ:DMA0_ACK:DMA1_ACK}  ] $fclk

Is it incorrect ?

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Scholar sampatd
Scholar
6,247 Views
Registered: ‎09-05-2011

Re: Associating DMA_REQ and DMA_ACK with clock pin

This is a known issue. 

 

It will be fixed in 2013.3 version.

 

Regards,

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Adventurer
Adventurer
3,574 Views
Registered: ‎08-05-2012

Re: Associating DMA_REQ and DMA_ACK with clock pin

Hello, I am using Vivado 2014.4 to view the "Ubuntu on Zedboard" reference design (which is actually just the ADV7511 reference design).  You said it will be fixed in 2013, but I still see these problem (which you say are actually false positives):

 

[BD 41-967] AXI interface pin /axi_spdif_tx_core/DMA_ACK is not associated to any clock pin. It may not work correctly.
[BD 41-967] AXI interface pin /axi_spdif_tx_core/DMA_REQ is not associated to any clock pin. It may not work correctly.
[BD 41-967] AXI interface pin /axi_i2s_adi/DMA_ACK_RX is not associated to any clock pin. It may not work correctly.
[BD 41-967] AXI interface pin /axi_i2s_adi/DMA_REQ_RX is not associated to any clock pin. It may not work correctly.
[BD 41-967] AXI interface pin /axi_i2s_adi/DMA_ACK_TX is not associated to any clock pin. It may not work correctly.
[BD 41-967] AXI interface pin /axi_i2s_adi/DMA_REQ_TX is not associated to any clock pin. It may not work correctly.

 

Any update on how to make these critical warnings go away?

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Adventurer
Adventurer
3,552 Views
Registered: ‎08-05-2012

Re: Associating DMA_REQ and DMA_ACK with clock pin

Hello Xilinx??
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Xilinx Employee
Xilinx Employee
3,479 Views
Registered: ‎07-30-2007

Re: Associating DMA_REQ and DMA_ACK with clock pin

It sounds like the IP might not have been packaged such that a pin is related to a clock. I'm not sure why these ACK and REQ signals would be an AXI Interface pin- that sounds incorrect.
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