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Observer enricodeiana
Observer
9,974 Views
Registered: ‎10-16-2014

Axi DMA in SG multi channel mode

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Hi everybody,

 

I'm trying to get the Xilinx example "xaxidma_multichan_sg_intr.c" to work, but I'm stuck with some issues (the code is attached to this thread for your convenience).

 

First of all: I'm using Vivado 2014.3 on Debian wheezy 64 bit and a Zybo (Digilent) as development board.

 

I have created a "loop back architecture", as the example requires.

Here it is an image of the architecture:

 

system.png

 

It should work like this: 2 packets are transmitted from the DMA to the 2 FIFOs. For each packet 2 Buffer Descriptors  (BDs) are used. The first packet is sent into channel 0, it is received by the channel 0 FIFO that sends it back to the DMA. Then, the CheckData() function checks whether the received and sent data are the same. Same should happen for the second packet which is sent into channel 1.

 

Now, the problems I got are the following (some of them were trivial and I fixed them, but others are not):

 

1) I had to modify these lines of code:

#ifdef XPAR_INTC_0_DEVICE_ID
#define RX_INTR_ID		XPAR_INTC_0_AXIDMA_0_S2MM_INTROUT_VEC_ID
#define TX_INTR_ID		XPAR_INTC_0_AXIDMA_0_MM2S_INTROUT_VEC_ID
#else
#define RX_INTR_ID		XPAR_FABRIC_AXIDMA_0_S2MM_INTROUT_VEC_ID
#define TX_INTR_ID		XPAR_FABRIC_AXIDMA_0_MM2S_INTROUT_VEC_ID
#endif

 into:

#ifdef XPAR_INTC_0_DEVICE_ID
#define RX_INTR_ID		XPAR_INTC_0_AXI_DMA_0_S2MM_INTROUT_VEC_ID
#define TX_INTR_ID		XPAR_INTC_0_AXI_DMA_0_MM2S_INTROUT_VEC_ID
#else
#define RX_INTR_ID		XPAR_FABRIC_AXI_DMA_0_S2MM_INTROUT_INTR //  <---
#define TX_INTR_ID		XPAR_FABRIC_AXI_DMA_0_MM2S_INTROUT_INTR //  <---
#endif

 

since in "xparameters.h" XPAR_INTC_0_DEVICE_ID is not defined we always go in the else branch. But XPAR_FABRIC_AXIDMA_0_S2MM_INTROUT_VEC_ID and XPAR_FABRIC_AXIDMA_0_MM2S_INTROUT_VEC_ID are not defined too, so I replaced them with the only 2 interrupt defines that I found on "xparameters.h": XPAR_FABRIC_AXI_DMA_0_S2MM_INTROUT_INT and XPAR_FABRIC_AXI_DMA_0_MM2S_INTROUT_INTR.

 

2) In the main() function after the first packet is sent and received, the CheckData() function checks whether the received packet on channel 1 and the sent packet on channel 0 are equal and, obviously, it fails. The opposite happens when the secondo packet on channel 1 is sent and received back. So, I modified these lines of code:

main(){

   ...

   Status = CheckData(MAX_PKT_LEN * NUMBER_OF_BDS_TO_TRANSFER, RxPacket1, PACKET0_DATA);

   ...

   Status = CheckData(MAX_PKT_LEN * NUMBER_OF_BDS_TO_TRANSFER, RxPacket0, PACKET1_DATA);

...
}

 into:

main(){

   ...

   Status = CheckData(MAX_PKT_LEN * NUMBER_OF_BDS_TO_TRANSFER, RxPacket0, PACKET0_DATA);

   ...

   Status = CheckData(MAX_PKT_LEN * NUMBER_OF_BDS_TO_TRANSFER, RxPacket1, PACKET1_DATA);

...
}

 Now, the first CheckData() succeed, while the second one is never executed because the execution stalls right after the second packet is sent in channel 1 (this issue is described below in point 3) ).

 

3) So, when the second packet is sent in the second channel (channel 1) the execution stalls in the while loop.

Here the code:

main(){

        ...

        /* Initialize flags before start transfer test  */
	TxDone = 0;
	RxDone = 0;
	Error = 0;

	/* Send a packet */
	Status = SendPacket(&AxiDma, TDEST1, TID1, PACKET1_DATA);
	if (Status != XST_SUCCESS) {
		xil_printf("Failed send packet\r\n");
		return XST_FAILURE;
	}

	/*
	 * Wait TX done and RX done
	 */
	while (((TxDone < NUMBER_OF_BDS_TO_TRANSFER) ||
		(RxDone < NUMBER_OF_BDS_TO_TRANSFER)) && !Error) {
		/* NOP */
	}

        ...

}

 

After some debugging I discovered that the reason the execution get stuck within the while loop is that the RxDone flag is never incremented, this happens because when the second packet is received on channel 1 the received packet interrupt does not fire.

So, the RxIntrHandler() and then the RxCallBack() functions are not executed for the second packet.

The TxDone flag is incremented to 2 (since there is a call to TxIntrHandler() and TxCallBack()) and the Error flag remains 0.

Does anybody have any clue on why is this happening?

 

 

Thank you,

 

 

 

Enrico

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1 Solution

Accepted Solutions
Visitor tan-nqd
Visitor
16,330 Views
Registered: ‎01-21-2015

Re: Axi DMA in SG multi channel mode

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Hi Enrico,

 

I am working on the exact same thing with you and also get that error. I notice the link: http://forums.xilinx.com/t5/Embedded-Development-Tools/Multi-channel-axi-dma-engine-implementation/td-p/312047 where drkow19 resolved it by setting High TDEST of Master port to 3 (no. channels - 1). You can try clicking on the AXIS interconnect 1 block and change the value of High TDEST to 1. It should solve the problem. 

 

Hope it helps.

Tan.

 

5 Replies
Visitor tan-nqd
Visitor
16,331 Views
Registered: ‎01-21-2015

Re: Axi DMA in SG multi channel mode

Jump to solution

Hi Enrico,

 

I am working on the exact same thing with you and also get that error. I notice the link: http://forums.xilinx.com/t5/Embedded-Development-Tools/Multi-channel-axi-dma-engine-implementation/td-p/312047 where drkow19 resolved it by setting High TDEST of Master port to 3 (no. channels - 1). You can try clicking on the AXIS interconnect 1 block and change the value of High TDEST to 1. It should solve the problem. 

 

Hope it helps.

Tan.

 

Observer enricodeiana
Observer
9,836 Views
Registered: ‎10-16-2014

Re: Axi DMA in SG multi channel mode

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Thank you Tan!
I didn't change High TDEST on the AXI4-Stream Interconnect with multiple slave and one master.
Now it works!

Enrico
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Visitor w.pram
Visitor
9,506 Views
Registered: ‎03-16-2015

Re: Axi DMA in SG multi channel mode

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Hi Enrico,

 

I also tried to use this multichannel DMA and face a problem. Other than the previous change of XPAR_FABRIC_AXI_DMA_0_S2MM_INTROUT_INTR, I also noticed that XPAR_AXIDMA_0_ENABLE_MULTI_CHANNEL is set to 0. The number of MM2S and S2MM are set to 1. I did set this value in block design (enable multi channel and use 16 channel max) and I expect that the tools will update these values automatically. I've changed XPAR_AXIDMA_0_ENABLE_MULTI_CHANNEL to 1 and use 2 channel for both MM2S and S2MM since the example perform 2 channel transfer but this does not work.

I use 1 AXI-Interconnect between PS and AXI DMA with 3 slave and 1 master. The DMA stream side is connected to fifo which form a loop-back connection. Can you explain in more details how did you manage to make your implementation work? Thanks

 

Wisnu

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Visitor zhangrao
Visitor
5,373 Views
Registered: ‎05-15-2015

Re: Axi DMA in SG multi channel mode

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Hi
I met the same problem with you.how do you make it works?
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Observer prakash.ganesh
Observer
1,154 Views
Registered: ‎09-12-2013

Re: Axi DMA in SG multi channel mode

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Hello

 

I did not understand what you had done to solve this issue.

 

could you please be more clearer.

 

I am trying to utilize the axi dma in sg mode and multichannel is enabled.

 

Regards

Prakash G

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