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Visitor matzun
Visitor
7,704 Views
Registered: ‎07-24-2014

Axi4s to video out can't lock XAPP792

Hello,

I'm developing system which requires AXI4S to Video Out IP Core. As base design I have used XAPP792. For about week I have been trying to connect Video Out IP Core right after VDMA Buffer (in master mode) - problem is really annoying - video won't lock on.  I know that this issue was described and answered many times on this forum, but nothing has helped.  I attached mhs file below.
 
On the oscylocope tuser and tlast signals are weird (tuser and tvalid - square wave 25Hz, tlast and tready - gnd).
It is an academic project which I'm obliged to finish in August. I look forward to hearing from you.

Thanks in advance.

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11 Replies
Xilinx Employee
Xilinx Employee
7,692 Views
Registered: ‎08-02-2011

Re: Axi4s to video out can't lock XAPP792

Hello,

 

So does the design work out of the box for you? What changes have you made to the design?

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Visitor matzun
Visitor
7,685 Views
Registered: ‎07-24-2014

Re: Axi4s to video out can't lock XAPP792

Hello,

 

first of all thank you for fast response. Below I described what I have done so far.

 

1. I have added FMC board with hdmi in/out (Avnet DVI/IO)  and have done video pass-through (mz_avnet_dvi_io) - works fine.

2. After that I have changed vtc configuration to detector/generator (to reproduce signals from camera, I needed vblank and hblank signals for osd as I recall) - works ok

3.  I have connected xsvi stream from camera to third vdma - also works.

 

After this steps I wanted to add two axi4s to video out IP's after two VDMA cores becouse I have to connect my own video processing core which have three xsvi inputs (two vdma and one from camera) and two xsvi outputs (inputs must be synchronous - axi4s to video out IP in master mode).

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Xilinx Employee
Xilinx Employee
7,620 Views
Registered: ‎08-02-2011

Re: Axi4s to video out can't lock XAPP792

Hello,

 

Hmm okay. Well here are the things I usually check:

- Clocks, resets, and clock enables

- Make sure to generate BOTH syncs and blanks out of VTC and connect them to AXI Stream to Video Out

- When VDMA or TPG in the path, use master mode for the AXIS to Video Out and do not connect the gen_clken to vtg_ce

- Check for locked status of VTC and AXI Stream to Video Out

- VTC generator should run at pixel clock that vid_io_clk is connected to on AXI Stream to Video Out

- Probe VTIMING, AXIS, and video out interfaces on the AXI Stream to Video out core to make sure you are getting properly formatted data on all interfaces

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Observer oosuna
Observer
7,491 Views
Registered: ‎08-25-2014

Re: Axi4s to video out can't lock XAPP792

You said do not connect gen_clken to vtg_ce when a VDMA is in the path. So, what do you do with that port. Should it always be enabled ? (tied high, when a VDMA in the path), that isn´t clear on the documentation.

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Xilinx Employee
Xilinx Employee
7,488 Views
Registered: ‎08-02-2011

Re: Axi4s to video out can't lock XAPP792

Yes, that's correct. When in master mode, just tie it high (it should have a default tieoff as such in IPI)
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Observer oosuna
Observer
7,471 Views
Registered: ‎08-25-2014

Re: Axi4s to video out can't lock XAPP792

Hi I'm developing a system which requires AXI4S to Video Out IP Core. As base design I have used XAPP792. For days I have been trying to connect Video Out IP Core right after VDMA Buffer- problem is really annoying - video won't lock on. I know that this issue was described and answered many times on this forum, but nothing has helped. I'm using Vivado 2014.2
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Observer oosuna
Observer
7,470 Views
Registered: ‎08-25-2014

Re: Axi4s to video out can't lock XAPP792

The VDMA appears to be configured correctly because it is not showing any errors and after checking it out with ChipScope I can see data flowing through all MM2S AXI Stream signals. I've got the S2MM channel setup as dynamic genlock master and the MM2S channel as dynamic genlock slave. The S2MM channel synchronizes frame with the Start of Frame on tuser(0), the MM2S channel is configured as Free running.

As far as I can tell from examples and posts on Xilinx Forums, the important connections/configurations for the AXI Stream to Video Out core are (which I have done):

-Using sync AND blank timing signals, along with active_video.
-Connecting VTG_CE to the timing controllers gen_clken port.
-Putting the Video Out core in slave timing mode (I’ve also tried the master timing mode).

However even after all of this the Video Out core never asserts a lock and always outputs 0's for timing signals and video data.
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Xilinx Employee
Xilinx Employee
7,465 Views
Registered: ‎08-02-2011

Re: Axi4s to video out can't lock XAPP792

Hello,

 

Thanks for doing your research!

 

One thing that seems to be confusing most folks about the core is the two different modes: master and slave. The general rule of thumb for most applications is:

 

- Master mode

  * Used if there is a VDMA in the design (or some other source that can accomodate arbitrary throttling on the AXIS interface)

  * Do not connect the VTG_CE to gen_clken port. This will prevent locking. Just tie VTG_CE high

- Slave mode

  * Used if there is no VDMA in the system or the system can not otherwise handle arbitrary throttling

  * The assumption is generally that there is no clock crossing happening in the datapath

  * In this mode, rather than throttling the AXIS interface, the AXI Stream to Video Out core 'throttles' the VTC generator by toggling the VTG_CE signal until they line upj

 

One other important assumption for either case: Your video output clock (on the Video Out to AXI Stream core) must be the correct output pixel clock rate! If your timing generator is generating 1080p60 video, your output clock (AND the clock that the VTC generator runs at) better be ~148.5MHz. Otherwise, you won't lock.

 

One last tip: for first bringup, just use the VTC generator in constant mode for the timing that you're testing. Once you bring up the system, you can add the AXI lite interface and add the ability to change the frame size or whatever. The reason I say that is because the VTC has a lot of registers to setup and a bit of a learning curve. Simplify by using constant mode for a standard frame size which will just work out of the box.

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Observer oosuna
Observer
7,448 Views
Registered: ‎08-25-2014

Re: Axi4s to video out can't lock XAPP792

I've attended your suggestions... I've tried both master & slave modes (following its particular set up) no improvement at all, the core won't lock. Also I've used the VTC generator in constant mode, the generator is configured to 1080p30 video, both my output and the VTC generator runs at is 74.25 MHz

Thanks for you help bwiec.
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Xilinx Employee
Xilinx Employee
2,753 Views
Registered: ‎08-02-2011

Re: Axi4s to video out can't lock XAPP792

Hmm, okay. A few other things:

- Make sure your VDMA size and stride registers are correct. In particular, HSIZE and STRIDE are in bytes per line, not pixels

- Probe the timing interface out of the VTC (going to the AXI Stream to Video) and make sure both vsync and vblank are toggling

- Check clocks, resets, clock enables in the post-implementation schematic

- Try increasing the AXIS2Vid buffer depth

 

If you want to post some data (hardware core connections/configurations, register dumps, etc), I'll take a look

www.xilinx.com
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Observer oosuna
Observer
2,743 Views
Registered: ‎08-25-2014

Re: Axi4s to video out can't lock XAPP792

Thank you so much for your time bwiec, the issue was solved. It was caused by an incorrect value on the STRIDE register.

Regards.
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