UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Contributor
Contributor
448 Views
Registered: ‎12-03-2018

BASE ADDRESS and HIGH ADDRESS in VIVADO 2018.2

Hi Everyone,

I am in a project with ARTIX 7,

When I create a Block IP and In Package IP, I can change Verilog Code,parameter,....,and Base Address 
and High Address.But In "Editor Address" the offset address and high address, it's the same with Package IP ??

ex : In Packet Ip : Base Address :FF00_0000     in Editor Address  Offset Addr : 44A0_0000   with range 4k
                             High                :FF00_0FFF                                  High Addr     44A0_0FFF

When I read/write data on SDK, the address FF00_0000,FF00_0FFF is not work,
I don't understand both case,
If i have an answer,please tell me,

Thank you very much,

vanloc,

 

0 Kudos
1 Reply
Moderator
Moderator
413 Views
Registered: ‎10-06-2016

Re: BASE ADDRESS and HIGH ADDRESS in VIVADO 2018.2

Hi @vanloc_tc1 

Could you elaborate and provide some screenshots of the issue? I mean, your description is bit confusing and is not easy to undestand. A good idea would be:

  1. Add screenshot of how address setting in the Package IP menu
  2. Add screenshot of address editor in the main design
  3. Add screenshot of the SDK view of the HDF file

Regards

 


Ibai
Don’t forget to reply, kudo, and accept as solution.
0 Kudos