05-29-2014 11:55 AM
This is a re-post in the correct (I hope), Embedded System Design section and I hope someone can help me with that.
In a post-XPS-to-VIVADO migration project, I am trying to create some sort of pseudo-OOC flow. Basically, I want to shorten the synth_design runtime (45-50 min) by delivering each of the IPs as an EDIF, and link them before place/route.
As a first step, I create a system_mb block design that encapsulates Microblaze, AXI periphericals etc, all these things that almost-never-change. Furthermore, all our proprietary modules are sitting on the AXI Lite, so I extended the AXI Interconnect's master AXI ports M_03_AXI to M_11_AXI external ports for that block design, and I think it would work ok, but I am getting the following critical warnings for all M_$$_AXI busses I made external. Now, assuming I followed AR#56609, all the steps till step 16 once I close the block design and reopen it, the warnings get different phrasing:
[BD 41-1287] Associated interface by name M_03_AXI not found for clock port /axi_lite_clk , where axi_lite_clk is an external port on that system_bd block design along with the M_$$_AXI interfaces.
i.e. I did set the ASSOCIATED_BUSIF on it to: M_03_AXI:M_04_AXI:M_05_AXI:M_06_AXI:M_07_AXI:M_08_AXI:M_09_AXI:M_10_AXI:M_11_AXI
What is missing here? Any properties that need to be set other than these? Does this block design need to be packaged as an IP?
Thanks a lot
05-29-2014 12:35 PM
03-14-2018 08:38 AM
Has anybody figured out how to fix this? I am seeing this myself now in Vivado 2017.4 in a Kintex 7 project on Windows 10 after I removed interfaces from the block design (see image below).