11-13-2017 05:10 AM
I am reading one xilinx pdf related to scaler and OSD, name is pg009_v_scaler.pdf. Can Anyone explain me the highlighted line in the image with the heading of AXI_VDMA0 configuration. My question is about addresses, Is both AXI_VDMA0 and AXI_VDMA1 will use same five frame locations of external memory or different locations? And How AXI_VDMA0 communicate/tells to AXI_VDMA1 for RW collisions?
Please go through the below attached image.
Thanks & Regards
11-13-2017 05:53 AM
11-13-2017 07:52 AM
Just a few things before answering to the question:
About you question:
You might want to look at the VDMA PG020 for information about how the VDMAs are synchronized. But basically you have input/output ports for the synchronisation.
Hope that helps,
11-15-2017 07:16 AM
Any update on this? Is it solved? If yes, could you mark the issue as solved by marking a response as solution?
Thanks and Regards,
11-15-2017 09:30 PM
Thanks for the reply, it's a bad news for me that xilinx is deprecate the scaler IP.
I went through the PDF which you mentioned but i am not understand it as well. Apologies for mismatch between question text and heading. Yes, you are correct both the VDMA are in the same FPGA. I just want to know that is both the VDMA will use same or different external locations?
Thanks and regards,
11-15-2017 11:53 PM
I am not really familiar with this design but my guess is that they are using the same memory but at different locations.