BOARD TO BOARD COMMUNICATION

[ssbillore]

Hi All,

I am reading one xilinx pdf related to scaler and OSD, name is pg009_v_scaler.pdf. Can Anyone explain me the highlighted line in the image with the heading of AXI_VDMA0 configuration. My question is about addresses, Is both AXI_VDMA0 and AXI_VDMA1 will use same five frame locations of external memory or different locations? And How AXI_VDMA0 communicate/tells to AXI_VDMA1 for RW collisions?

Please go through the below attached image.

Thanks & Regards

Sourabh

[balkris]

please refer this post
https://forums.xilinx.com/t5/Embedded-Processor-System-Design/Basic-doubts-about-genlock-and-fsync-in-VDMA/td-p/677235

[florentw]

Hi @ssbillore,

Just a few things before answering to the question:

• The OSD and the scaler IP are deprecated (not supported anymore by Xilinx). You might want to use the video mixer and video processing subsystem instead.
• Just to be clear, the text you are showing is not talking about board to board. The 2 VDMAs are in the same FPGA.

About you question:

You might want to look at the VDMA PG020 for information about how the VDMAs are synchronized. But basically you have input/output ports for the synchronisation.

Hope that helps,

Regards,

Florent

[florentw]

Hi @ssbillore,

Any update on this? Is it solved? If yes, could you mark the issue as solved by marking a response as solution?

Thanks and Regards,

Florent

[ssbillore]

Hi @florentw,

       Thanks for the reply, it's a bad news for me that xilinx is deprecate the scaler IP.

I went through the PDF which you mentioned but i am not understand it as well. Apologies for mismatch between question text and heading. Yes, you are correct both the VDMA are in the same FPGA. I just want to know that is both the VDMA will use same or different external locations?

Thanks and regards,

sourabh

[florentw]

HI @ssbillore,

I am not really familiar with this design but my guess is that they are using the same memory but at different locations.

Kind Regards,

Florent