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Visitor
Visitor
1,280 Views
Registered: ‎09-01-2016

BOARD TO BOARD COMMUNICATION

Hi All,

I am reading one xilinx pdf related to scaler and OSD, name is pg009_v_scaler.pdf. Can Anyone explain me the highlighted line in the image with the heading of AXI_VDMA0 configuration. My question is about addresses, Is both AXI_VDMA0 and AXI_VDMA1 will use same five frame locations of external memory or different locations? And How AXI_VDMA0 communicate/tells to AXI_VDMA1 for RW collisions?

Please go through the below attached image.

 

Thanks & Regards

Sourabh

 

 

AXI_VDMA0  - AXI_VBMA1.png

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Xilinx Employee
Xilinx Employee
1,265 Views
Registered: ‎08-01-2008

please refer this post
https://forums.xilinx.com/t5/Embedded-Processor-System-Design/Basic-doubts-about-genlock-and-fsync-in-VDMA/td-p/677235
Thanks and Regards
Balkrishan
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Moderator
Moderator
1,246 Views
Registered: ‎11-09-2015

Hi @ssbillore,

 

Just a few things before answering to the question:

  • The OSD and the scaler IP are deprecated (not supported anymore by Xilinx). You might want to use the video mixer and video processing subsystem instead.
  • Just to be clear, the text you are showing is not talking about board to board. The 2 VDMAs are in the same FPGA.

About you question:

You might want to look at the VDMA PG020 for information about how the VDMAs are synchronized. But basically you have input/output ports for the synchronisation.

 

Hope that helps,

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
1,182 Views
Registered: ‎11-09-2015

Hi @ssbillore,

 

Any update on this? Is it solved? If yes, could you mark the issue as solved by marking a response as solution?

 

Thanks and Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor
Visitor
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Registered: ‎09-01-2016

Hi @florentw,

       Thanks for the reply, it's a bad news for me that xilinx is deprecate the scaler IP.

I went through the PDF which you mentioned but i am not understand it as well. Apologies for mismatch between question text and heading. Yes, you are correct both the VDMA are in the same FPGA. I just want to know that is both the VDMA will use same or different external locations?

 

 

 

Thanks and regards,

sourabh

 

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Moderator
Moderator
1,158 Views
Registered: ‎11-09-2015

HI @ssbillore,

 

I am not really familiar with this design but my guess is that they are using the same memory but at different locations.

 

Kind Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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