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Observer
Observer
8,141 Views
Registered: ‎02-27-2009

Bad UART frequency when exporting/importing block design in Vivado

I have a block design with a ZYNQ processing system in Vivado (2014.4). I am using TCL export function to transfer the block desing to another project. After executing the script in the target project, the UART baudrate (PS7 UART seems to bee wrong). The Summary Report of the ZYNQ7 Processing System (attached) shows a UART frequency of 1600 MHz which is obviously wrong (should be 100 Mhz). project_1\project_1.srcs\sources_1\bd\system\ip\system_processing_system7_0_0\system_processing_system7_0_0.xml and project_1\project_1.srcs\sources_1\bd\system\ip\system_processing_system7_0_0\system_processing_system7_0_0.xci have entries for PCW_UART_PERIPHERAL_FREQMHZ and PCW_ACT_UART_PERIPHERAL_FREQMHZ for 1600 MHz. Can you confirm that this is a bug in Vivado? Is there a solution?
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Xilinx Employee
Xilinx Employee
8,101 Views
Registered: ‎08-02-2007

hi,

 

would that be possible to share the project and the script to further look into this problem?

 

i have tried a quick system at my end and do not see problem.

 

i have attached the .xci and xml.

 

--hem

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Observer
Observer
8,043 Views
Registered: ‎02-27-2009

Please find attached the broken Vivado Project.

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Xilinx Employee
Xilinx Employee
8,032 Views
Registered: ‎08-02-2007

hi,

 

this looks to be targeting to a zybo board, do correct me if i am wrong.

 

i tried to bring up this project, however there are a few custom IP's existing in it. i am not able to build it because of them.

 

would that be possible to remove the custom IP's and just provide a system with xilinx based IP's so that we can replicate the problem?

 

--hem

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