cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
petervuto
Observer
Observer
1,938 Views
Registered: ‎07-08-2017

Booting petalinux 2016.1 with boot level 1 gives no output, but level 3 works

Jump to solution

This is my first time doing anything like this so I'm completely out of my depth.

 

Anyway, I downloaded the premade  2016.1 ZedBoard BSP and used it to built petalinux. Went with default settings in the graphical config thing, and took the download.bit and zynq_fsbl.elf files that were generated in images/linux presumably from the BSP. 

 

When I write "watch screen /dev/ttyACM0 115200" I can see fpga output when running bare-metal stuff. I'll call this the fpga console from now on.

 

When I run "petalinux-boot --jtag --prebuilt 3", I get a nice login screen on the fpga console, I can ls the root of the filesystem and see bin boot and other neat stuff. So that works. .

prebuilt 3 output:

 

INFO: Append dtb - /workdir_no_spaces/petalinux/Avnet-Digilent-ZedBoard-2016.1/pre-built/linux/images/system.dtb and other options to boot zImage
INFO: Launching XSDB for file download and boot.
INFO: This may take a few minutes, depending on the size of your image.
rlwrap: warning: your $TERM is 'xterm' but rlwrap couldn't find it in the terminfo database. Expect some problems.: Inappropriate ioctl for device
INFO: Configuring the FPGA...
INFO: Downloading bitstream to the target.
INFO: Downloading ELF file to the target.
INFO: Downloading ELF file to the target.

INFO: SOC Silicon version is 1.0.

 

 

 

However, when I do "petalinux-boot --jtag --prebuilt 1", the fpga console doesn't react.

prebuilt 1 output: 

 

INFO: Launching XSDB for file download and boot.
INFO: This may take a few minutes, depending on the size of your image.
rlwrap: warning: your $TERM is 'xterm' but rlwrap couldn't find it in the terminfo database. Expect some problems.: Inappropriate ioctl for device
INFO: Configuring the FPGA...
INFO: Downloading bitstream to the target.
INFO: Downloading ELF file to the target.

INFO: SOC Silicon version is 1.0.

 

 

Questions:

1. What could I be doing wrong in the second case?

2. The help file says that boot level 3 is kernel only, boot level 1 is with bitstream. When I launch at level 3, I still see a "downloading bitstream.." step (and it takes a solid 5-10 seconds as usual!), what's up with that?

0 Kudos
1 Solution

Accepted Solutions
petervuto
Observer
Observer
3,179 Views
Registered: ‎07-08-2017
On further reading, it seems that I had misunderstood level 1 compared to level 3. The manual says that level 3 does more than level1.
Level 1: Download the prebuilt FPGA bitstream
Level 3: For Zynq-7000: Download the prebuilt FPGA bitstream and FSBL and boot the prebuilt u-boot and boot the prebuilt kernel on target.

If all level 1 does is download a bitstream, then no wonder the fpga doesn't respond, it's not getting any commands after all. Or at least that's how I understand it.

View solution in original post

0 Kudos
1 Reply
petervuto
Observer
Observer
3,180 Views
Registered: ‎07-08-2017
On further reading, it seems that I had misunderstood level 1 compared to level 3. The manual says that level 3 does more than level1.
Level 1: Download the prebuilt FPGA bitstream
Level 3: For Zynq-7000: Download the prebuilt FPGA bitstream and FSBL and boot the prebuilt u-boot and boot the prebuilt kernel on target.

If all level 1 does is download a bitstream, then no wonder the fpga doesn't respond, it's not getting any commands after all. Or at least that's how I understand it.

View solution in original post

0 Kudos