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Adventurer
Adventurer
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Registered: ‎03-16-2010

Bug Report: Memory inferral macro is broken

I have posted multiple threads hoping to solve my memory corruption problems when writing to inferred RAM and using netgen I figured out what is going wrong.

 

Information:

- Used Xilinx tools 11.5 and 12.1

- Memory inferred using HDL and CoreGen

 

Expected result:

4 RAMB36E1 blocks should be coupled together to form one 16KB RAM with 32-bit wide data in and data out. RAM mode is write-first. Because I needed to connect the RAM to a MicroBlaze, byte-write enable was needed.

 

Actual result:

Resulting RAM component works fine in read mode but writing anything but full words results in data corruption in other bytes of the target word.

 

More information:

The 4 RAM blocks are used in parallel: each byte of a word is divided over the 4 RAM blocks. However, each RAM has ECC memory which is disabled by default. This is a spare bit (or 4 bits when using 32-bits per RAM) which can be used to store data if the ECC mechanism is disabled.

 

The macro connects 8 bits of the first byte to the first RAM and the connects the first bit of the second byte to the ECC bit. The second RAM receives bit 2 to 8 of the second byte and then the first two bit from byte three. And so on.

 

The resulting memory might use byte-write enables but will never work properly this way. See the schematic below for some clarification.

 

|-----------------|-----------------|-----------------|-----------------|

|      RAM 0      |      RAM 1      |     RAM 2       |      RAM 3      |

|0|1|2|3|4|5|6|7|E|0|1|2|3|4|5|6|7|E|0|1|2|3|4|5|6|7|E|0|1|2|3|4|5|6|7|E|

|-----------------|-----------------|-----------------|-----------------|

|0|1|2|3|4|5|6|7|8|

                  |9|10|11|12|13|14|15|16|17|

                                    |18|19|20|21|22|23|24|25|26|

                                                      |27|28|29|30|31|X|X|X|X|

 

Expected resulting RAM (inferred) and its connections:

 

|-----------------|-----------------|-----------------|-----------------|

|      RAM 0      |      RAM 1      |     RAM 2       |      RAM 3      |

|0|1|2|3|4|5|6|7|E|0|1|2|3|4|5|6|7|E|0|1|2|3|4|5|6|7|E|0|1|2|3|4|5|6|7|E|

|-----------------|-----------------|-----------------|-----------------|

|0|1|2|3|4|5|6|7|X|

                  |8|9|10|11|12|13|14|15|X|

                                    |16|17|18|19|20|21|22|23|X|

                                                      |24|25|26|27|28|29|30|31|X|

 

My other threads:

http://forums.xilinx.com/t5/EDK-and-Platform-Studio/Problem-with-inferred-RAM-blocks/m-p/70063

http://forums.xilinx.com/t5/EDK-and-Platform-Studio/Inferred-RAM-and-write-enable-signals/m-p/69268

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