12-05-2012 10:24 AM
I am working on an MPMC system on a Spartan-6 LX150T with a single VFBC write and a single VFBC read port. I am running at a data rate that is about half of what is reported in the MPMC data sheet. (800 MB/s). My data rate is about 572 MB/s.
I am looking at the generated .mhs and mpmc_0_wrapper.v files and notcied that the C_PIM0_DATA_WIDTH parameter is set to 32. I would have expected this to be 64 for VFBC based on the excerpt below from MPMC data sheet, page 222.
The VFBC PIM uses the NPI interface of the MPMC, therefore the latency and throughput of the VFBC PIM is
similar to the NPI PIM. The maximum throughput of the VFBC PIM is 95.2% of the NPI PIM throughput (see
Table 94, page 211). The VFBC uses 32-word bursts and 64-bit NPI interface only; consequently, only those
configurations from Table 94, page 211 are valid for the VFBC numbers.
Am I interpreting this wrong?
The reason I am doing a deeper dive into the MPMC and VFBC instance definitions is an issue in simulation where I see the VFBC_Wd_Full flag asserted. I am trying to track down where my BW estimation or understanding is mistaken.
12-05-2012 10:42 AM
12-05-2012 11:28 AM
12-05-2012 11:41 AM
I have a related question on MPMC - regarding the C_PORT_CONFIG parameter. This allows us to select between Unidirection/Bidirectional ports of various widths. How does this parameter relate to:
A) The VFBC 64-bit NPI width parameter in the datasheet (see op).
B) The C_PIM_DATA_WIDTH parameter
C) The C_VFBC0_RDWD_DATA_WIDTH parameter