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Visitor
Visitor
3,847 Views
Registered: ‎07-28-2011

CLK/IBUFDS problem while integrating an EDK module

Hi,

 

I want to integrate an EDK-Module into my existing design. The problem I have is that I can not use the onboard (diff.) clock input sysclk since this is already used. The error message is as follows:

 

ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a   single IOB component because the site type selected is not compatible. 
   Further explanation:   The component already has an input slave buffer.   Symbols involved:   PAD symbol "sysclk_n_0" (Pad Signal = sysclk_n_0)   SlaveBuffer symbol   "fmc126/sip_mac_engine_0/mac_engine_inst/brd_clocks_inst/pll0_inst/clkin1_buf   /SLAVEBUF.DIFFIN" (Output Signal =   fmc126/sip_mac_engine_0/mac_engine_inst/brd_clocks_inst/pll0_inst/clkin1_buf/   SLAVEBUF.DIFFIN)   SlaveBuffer symbol "Inst_Ctrl/ibufgds_0/SLAVEBUF.DIFFIN" (Output Signal =   Inst_Ctrl/ibufgds_0/SLAVEBUF.DIFFIN)
ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a   single IOB component because the site type selected is not compatible. 
   Further explanation:   The I/O component already owns an input buffer.   Symbols involved:   PAD symbol "sysclk_p_0" (Pad Signal = sysclk_p_0)   DIFFAMP symbol   "fmc126/sip_mac_engine_0/mac_engine_inst/brd_clocks_inst/pll0_inst/clkin1_buf   /IBUFDS" (Output Signal =   fmc126/sip_mac_engine_0/mac_engine_inst/brd_clocks_inst/pll0_inst/clkin1)   DIFFAMP symbol "Inst_Ctrl/ibufgds_0/IBUFDS" (Output Signal = Inst_Ctrl/CLK)


How can I work around this? Can I adapt the EDK module in XPS in this way that the input clock is not buffered or should I generate another clock for driving my embedded module?
I am using Xilinx ISE 13.2 and the ML605!

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3 Replies
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Visitor
Visitor
3,829 Views
Registered: ‎07-28-2011

Nobody has an idea?

Maybe you have some resources: links, topics... I should go through!

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Instructor
Instructor
3,827 Views
Registered: ‎07-21-2009

You might have better luck in the EDK forum.  You might be better off opening a webcase for support.

 

-- Bob Elkind

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Observer
Observer
3,809 Views
Registered: ‎11-04-2009

I've had this problem before, both in EDK designs and VHDL-only things.

If you are using a DCM (which is put into the EDK design by default), you can't connect the input clock to both the DCM and other things in your system in general, I believe.

There are a few different ways you can handle this.

 

The simplest would probably be to take the clock output from the DCM within your EDK system and bring it back to your top level by simply adding a clock out port to your EDK project's system.mhs file.Then you can use this as the clock in your top level design.

Even if you are multiplying/dividing the clock to the different frequency, the DCM has a clock output which is the same frequency as the input clock (If I remember right it's called CLK0). This is what you are supposed to use with the rest of your system, rather than the input clock itself.

 

You could also erase the DCM from the EDK part (just erase or comment out the clock manager block in system.mhs), and instantiate it in your top level ISE project, and then put the output clock into the clock input of your EDK system, and then modify system.mhs so that the components needing clocks within EDK just take the clock that is input on the EDK component's port, rather than the output of the clock manager that you have just erased.

 

Another possibility would be to skip the DCM altogether, and just replace all of the clocks in your system.mhs with your raw clock input, if you don't want or need to do any frequency multiplying or division. In my Virtex 4 PPC project I've been using, I do exactly this with no trouble.

 

Hope that helps!

 

Steve

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