08-06-2009 08:09 AM
I have created test projectin EDK. I have generated squere CORDIC root pcore with CoreGen. Options of this pcore: Square Root, Parallel, No Pipelining, Unsigned Fraction, Radians, No Override, RDY, X_Out, CE, ND, Round Pos Inf, Input width 32-bits, Output width 17-bits. This pcore I connected with "Create or Import Peripheral wizard", did FSL bus. In attached file you can see VHDL code. Port map is such:
x_in => FSL_S_Data, nd => FSL_S_Exists, x_out => data_from_sqrt, rdy => FSL_M_Write, clk => FSL_Clk, ce => FSL_S_Exists);
In C application I put variable and try to get result from this core, but result is incorrect or possible I display in false. I need to operate with floating point. In this example I put and get integer number, but if I operate with float numbers, result is allways zero.
Bellow you can see output results and C code:
int val = 27, res; //float val2=0.34f, res2; printf("Input value is: %d\n\r", val); putfslx(val, 0, FSL_NONBLOCKING); getfslx(res,1,FSL_NONBLOCKING); printf("Result is: %d\n\r", res);
09-08-2009 01:41 PM
Does this AR http://www.xilinx.com/support/answers/32072.htm match what you were seeing?
I have downloaded your project. Unfortunately, project is created with ISE 11. I’m using 10.1.3, CORDIC version is 4. My version is CORDIC 3. I have used your sqr_tb.vhd file. In attached file you can find some simulation pictures with corresponding test bench files. Signals of data are in hexadecimal format.
2_test.vhd is almost the same as your test bench and 2_diagram.jpeg is corresponding diagram. Please take look at this diagram. Output is changing just 4 times:
IN x0 -> OUT x0
IN x100000 -> OUT x400
IN x80040F -> OUT xB50IN x4 -> OUT x2
IN x20 -> OUT0 ????
Result by this input (2_test.vhd) is not so bad. But please look at 3_diagram.jpeg and 3_test.vhd. If input value first time is small output is zero always too!
Most interest is 5_diagram.jpeg. This diagram corresponds your send project, but value changes just one time.
Also, I attaché full project (almost the same as your just for version 10).
Please explain what I'm doing wrong?
08-06-2009 11:23 AM
08-06-2009 01:57 PM
You say it goes wrong with floating point numbers,
I think that is the clue, I dont' think the cordic understands IEEE floating point numbers.
the cordic is expecting unsigned fractional numbers, not floating point numbers.
you need to stay to fixed pint numbers ( i.e. integers with an imaginary decimal point )
08-06-2009 10:59 PM
Floating point numbers is another questions, most important are integer numbers, because posted result I think is not right.
Maybe sequence of connected port numbers in vhd is not right? ((0 to 15)...(15 downto 0)...)
08-07-2009 10:32 AM
Big endian, little endian is a good question,
Would a simulation be possible to give you more visibility ?
08-10-2009 10:11 AM
thank you for your reply.
to change the range of signals of square root pcore I use this one:
FSL_M_Data <= data_from_sqrt'reverse_range & "000000000000000";
FSL_M_Data <= "000000000000000" & data_from_sqrt;
But EDK doesnt understand attribute reverse_range
08-10-2009 11:20 AM
I don't have EDK on this machine,
I was wondering, your cordic number is unsigned I assume. ( Sqrt of a negative number not easy ) so should it not be natural not integer ?
Your example, if it's VHDL, what is meant by "000000000000000", do you not have to put a 'b' in front to make it binnary. may be I just do it out of habit.
FSL_M_Data <= B"000000000000000" & data_from_sqrt ;
what's the simulation say is happening ? is your data coming out of the cordic, this would answer is it the sending the data or receiving it.
I also assume the cordic is not instantanious, so you are handeling the hand shaking else where.
sorry, as I say no EDK on this machine so could be way off mark here.
08-11-2009 01:21 AM
Thank you for your help! This sqrt pcore should replace mathematical operation in C application (from math.h library), Actually I operate with floating point numbers, so that target would be not integer numbers, but for discovers integer range is enough.
I did some simulations with ISE. Bellow are my results.
Version 1 (more simple version):
signal data_from_sqrt : std_logic_vector(0 to 16);
your_instance_name : saknis_1 port map ( x_in => FSL_S_Data, nd => FSL_S_Exists, x_out => data_from_sqrt, rdy => FSL_M_Write, clk => FSL_Clk, ce => FSL_S_Exists);
FSL_S_Read <= FSL_S_Exists;
FSL_M_Data <= B"000000000000000" & data_from_sqrt;
FSL_M_Control <= '0';
if you see here FSL_S_Data input is connected directly to sqrt pcore (x_in). FSL_M_Data allways is zero. But if I send x_in => B"00000000000000000000000000011111", FSL_M_Data gives 6. (sqrt(31)~6 -round POS Inf).
signal dataA : std_logic_vector(31 downto 0);
The_SW_accelerator : process (FSL_Clk) is
for i in FSL_S_Data'reverse_range loop
dataA(i) <= FSL_S_Data(i);
end process The_SW_accelerator;
...-- no changes
x_in => dataA,
hereI have added one process to do revers. Result is this:
Result is very bad. Also, no matter what to use reverse_range or range attribute.
What is incorrect in this code?
08-11-2009 01:37 AM
Sorry don't have EDK, but have you tried an ISE or modelsim simulation of the cordic, to see what it's doing ?
08-11-2009 01:55 AM
08-11-2009 04:38 AM
do you have the waveforms ? what is the timing form writting into the cordic till the answer gets out ?
08-11-2009 06:00 AM
In attache file is wave form.
Delay of processing data is ~ 425 ns
08-11-2009 08:18 AM
my limited knowledge of the FSL bus , and this waveform looks strange.
I understand FSL is a single direction bus. data goes into it on the master side, out on the slave side.
also read and write are active high.
So looking at your diagram, you have data on the _s before the _m, your write is active after your read, and the write comes part way through what you indicate is your cycle.
Can I make a suggestion, try a simple register or ram on the FSL bus in stead of the cordic, and compare how that simulates.
The FSL spec is here, look at page 5 for the read and write operatinos you would expect to see.
08-11-2009 11:54 AM
Hmmz, I'm a bit confused now. FSL interface is generated of EDK wizard and looks so:
FSL_Clk : in std_logic; FSL_Rst : in std_logic; FSL_S_CLK : out std_logic; FSL_S_READ : out std_logic; FSL_S_DATA : in std_logic_vector(0 to C_INPUT_DWIDTH-1); FSL_S_CONTROL : in std_logic; FSL_S_EXISTS : in std_logic; FSL_M_CLK : out std_logic; FSL_M_WRITE : out std_logic; FSL_M_DATA : out std_logic_vector(0 to C_OUTPUT_DWIDTH-1); FSL_M_CONTROL : out std_logic; FSL_M_FULL : in std_logic
As you see_M and _S ports are given in different way: some of then are input, some are output, no matter either _M or _S.
To understand more about FSL and MB I have read this link.In this project FSL interface is in attached file.
08-11-2009 01:10 PM
So, not having EDK or Impluse, I'm at a bit of a loos end,
but I see in your vhdl you have two FSL bus's,
p_cpu_proc_output_stream_if and p_cpu_proc_input_stream_if.
so the signals to them are ?
I'd expect the p_cpu_proc_output to be the data written to the cordic, and some time later when the cordic is ready, then the p_cpu_proc_input to read the cordic's output data. I can't see that in the diagram you posted.
I'm just about on the limit of what I can do for you here, I might well be pointing you in the wrong direction,
08-12-2009 06:36 AM
I have read several times fsl datasheet. FSL bus is one direction. One FSL bus has to be conencted to MB master and pcore slave, second FSL bus has to be connected to pcore master and MB slave. Letters _M and _S in definition of signals (in FSL datasheer) means master and slave device. For example FSL_S_Data is output for MB, but is input for pcore. Because need to connect pcore to FSL FSL_S_Data is input for pcore. and the same is with other ports.
Please correct me if I lie... :).
So, my diagram is correct, one question is why do I get input just after reverse of data input (also this input generates not correct result, because it's reversed) otherwise result is zero
08-12-2009 07:57 AM
Also, I cannot believe that FSL bus is so complicate question. Cordic and another pcores are standart products of CoreGen tools, FSL bus is recomended of Xilinx to be use, and now we discuss about signal waveforms. I hoped to achieve fast results and now 1 month try to create wrapper of CORDIC, FFT and multiplier generated with CoreGen. Could somebady maybe send me to email complete simple project this topic about. I need to use correct CORDIC, multiplier of FFT?
Thank you very much
08-12-2009 10:45 AM
please remeber I have no contact with Xilinx, just an understanding employer,
the reason I ask for waveforms is they are the actual hardware.
Although it's well hidden, you are creating hardware in CoreGen so looking at the hardware is a good sanity check.
As for a month to learn, not bad going, where did you start from.
Big suggestion is if you are having this much problem, go on a course for coregen, there are many , including some on the web, which are at a price you might accept.
08-13-2009 11:41 PM
I have simulated alone sqrt CORDIC without any FSL. I don't understand exaclty why, but result in output Cordic get then if value of input achieve "100000000000000" (input='1') (>16384 in decimal). If input have such or higher value, CORDIC gives correct result. What does it mean??
08-15-2009 06:23 AM
Looks like CORDIC square root has bug...
How could I send incorect input data if this pcore has just X_IN, ND and RESET. ND I send allways, but pcore just "ignore" X_in less than "100000000000000".
Please help me
08-24-2009 09:19 AM
Ok, so I looked at cordic in core builder, and cordic is configurable by you ,
how have you configured it ?
unsigned or signed inputs ? fractional or integer ? what is the pipe line delay specified ?
and for future interest, what is the maximum clock speed it will work at .
I'd like to see the traces in hex, and the clock also.
BTW: have you checked the polarity of the enables etc ?
08-24-2009 12:48 PM
I use such configuration:
I don't use pipe line, so that no delay is specified.
I work with ML402 board and MicroBlaze is specified to use 100 MHz clock.
Also, attached is diagram
08-24-2009 02:07 PM
even with no pipe lining, there is still a latency through the cordic of 2 with the input and output registers.
I don't know about your Aclr, I only have sclr as an option.
I presume the phase format is greyed out for you as well,as obviously sqr does not have phase.
I presume A is Xin and B is Xout.
but I must admit I'm a bit stumped.
try putting in only one data sample , the number 32 is a good one, i.e. only newdata high for one clock. I'd expect to see ready high for one clock also, alligned to the data out.
08-25-2009 10:46 AM
You are right: A is X_IN, B is X_OUT. I did SCLR like you said you are using.
I attache diagram where you can see that trashold of sensitive of sqrt pcore is >4000 (hexadecimal) (14th bit is 1).
What does it mean? I can give full project
08-27-2009 03:04 PM
OK, now give cordic time to start up.
i.e. give it clock etc, with CE active
Wait a few clocks, and hit it with a reset.
wait a few more clocks and give it your one clocks worth of data. and wait for the ready to come out.
08-31-2009 01:43 PM
I did some difference in the simulation file. You can see it bellow. But it looks like no matter what to send and when to send:
09-01-2009 08:55 AM
well I got a few minutes to myself, and thought I'd put the cordic design to a quick test.
All numbers in base 10, unsigned decimal
I put in 1048576, and I get out 1024,
I put in 1048575, and I get out 1023
I put in 1048577, and I get out 1024
I put in 16928, and I get out 130
all as expected.
I think you just need to look at what number base you are looking at in the simulation.
BTW: How did you paste those wave pictures in ?
09-01-2009 12:41 PM
but please try put small numbers like 4, 32,100..
base of this topic is that cordic doesnt work with small numbers. It gives output values if input (in binary form) is greater than b"10000000000000"
09-01-2009 01:20 PM - edited 09-01-2009 01:44 PM
sorry , yep I did that also
I put in decimal 3, I get out decimal 1
I put in decimal 4, I get out decimal2
I put in decimal 8, I get out decimal 2
i put in decimal 9, I get out decimal 3
I put in decimal 32, I get out decimal 5
Could I ask, What format / radiux are you viewing the numbers in on the simulator ?
If you look at your example, you put in I think 4220 hex ( which is 16928 unsigned decinal ) . sqrt of 16928 is 130.1 in decimal, which in hex is 82. You have 83, which I think is the way you have rounding set ( pos inf ).
09-02-2009 08:31 AM
You need to save your snapshot as a file and then click "Add Attachment" link at the bottom of the message window.
BTW: How did you paste those wave pictures in ?