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Scholar watari
Scholar
1,622 Views
Registered: ‎06-16-2013

CRITICAL WARNING: [BD 41-1265] Different peripherals

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Hi all

 

I'd like to know whether the following CRITICAL WARNING is well known and unresolved problem in 2016.4 or NOT.

 

I'm probably sure that I can ignore the following CRITIAL WARNING.

 

The address map is same between /microblaze_0_local_memory/dlmb_bram_if_cntlr/SLMB/Mem and /processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM.

However their bus category are different. One is AXI. Other is LMB.

 

[Question]

Q1) Can I ignore the following CRITICAL WARNING ?

Q2) If Q1's answer is NO, how do I resolve it ?

Q3) If Q2's answer is YES, when does Xilinx resolve it ? 2017.4 ? or later ? or No plan ?

 

[Warning Message]

CRITICAL WARNING: [BD 41-1265] Different peripherals </microblaze_0_local_memory/dlmb_bram_if_cntlr/SLMB/Mem> and </processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM> are mapped into related masters </microblaze_0/Data> and </axi_vdma_0/Data_MM2S> at the same offset
CRITICAL WARNING: [BD 41-1265] Different peripherals </microblaze_0_local_memory/dlmb_bram_if_cntlr/SLMB/Mem> and </processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM> are mapped into related masters </microblaze_0/Data> and </axi_vdma_1/Data_MM2S> at the same offset

 

Thank you.

Best regards,

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Moderator
Moderator
2,249 Views
Registered: ‎11-09-2015

Re: CRITICAL WARNING: [BD 41-1265] Different peripherals

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Hi @watari,

 

From you project, I confirm that you shouldn't have any issue as there is no link between both memory (ie. the MB cannot access the PS DDr in your case).

 

If you want to remove this warning, you can change the address for the MB local memory:

MB memory.PNG

 

However this is not a requirement.

 

Best Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
1,596 Views
Registered: ‎11-09-2015

Re: CRITICAL WARNING: [BD 41-1265] Different peripherals

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Hi @watari,

 

Could you share a screenshot of you BD? I might help to understand

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Scholar watari
Scholar
1,574 Views
Registered: ‎06-16-2013

Re: CRITICAL WARNING: [BD 41-1265] Different peripherals

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Hi @florentw

 

Full screenshot has non discrosure ifnromation.

I'd like to send it directoly.

Can I do it ?

 

If you don't need fully information, I already shown it on my previous message.

 

Thank you.

Best regards,

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Moderator
Moderator
1,526 Views
Registered: ‎11-09-2015

Re: CRITICAL WARNING: [BD 41-1265] Different peripherals

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Hi @watari,

 

I don't think this is an issue. You are just accessing the same memory with your processor and your VDMAs. You just have to be aware of it when reading/writting to the memory.

Also make sure your data/instruction are not using the memory you will use for the vdma.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Scholar watari
Scholar
1,523 Views
Registered: ‎06-16-2013

Re: CRITICAL WARNING: [BD 41-1265] Different peripherals

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Hi @florentw

 

I don't think it.

Please refer the attached picture.

"microblaze_0_local_memory" which has SRAM as address 0x00 -, is only for Microblaze.

I think that it can not access via VDMA.

 

Do you need hdf file ? "hdf" file has more detail information...

 

Thank you.

Best regards,

 

microblaze-localmemory.png
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Moderator
Moderator
1,517 Views
Registered: ‎11-09-2015

Re: CRITICAL WARNING: [BD 41-1265] Different peripherals

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Hi @watari,

 

I would need to full project to confirm.

 

However, it should have access to the DDR via the M_AXI_DP interface. And this DDR memory can still be used for MB data memory (depending on your settings in the linker file).

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Moderator
Moderator
2,250 Views
Registered: ‎11-09-2015

Re: CRITICAL WARNING: [BD 41-1265] Different peripherals

Jump to solution

Hi @watari,

 

From you project, I confirm that you shouldn't have any issue as there is no link between both memory (ie. the MB cannot access the PS DDr in your case).

 

If you want to remove this warning, you can change the address for the MB local memory:

MB memory.PNG

 

However this is not a requirement.

 

Best Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos