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Visitor 0004231010
Visitor
17,460 Views
Registered: ‎04-07-2009

Cache and DDR SDRAM

Hello I really need help and I appreciate any suggestion. Thank you for any answer.

 

In my work I need to send audio data to another computer through internet. The audio data

are stored in DDR SDRAM. It works fine. But when I turn on cache it doesn´t work anymore.

 

Some facts:

I´m using ML403 platform. There is Virtex-4, xc4vfx12 and I´m using PowerPC processor.

Also I´m using xilkernel and lwip library. My memory are mapped -

 

DDR SDRAM 0x00000000 - 0x03ffffff

BRAM 0xffff0000 - 0xffffffff

 

so I´m using -

 

XCache_EnableICache(0x80000001);
XCache_EnableDCache(0x80000001);

 

to activate the caching. I discovered that the program works when I use -

 

XCache_EnableICache(0x80000001);
XCache_EnableDCache(0x00000001);

 

so it means that the problem is when I use data cache for DDR SDRAM. But

I really need to cache this memory.

 

It´s very strange becouse I use data cache for DDR SDRAM before in another programs

(also with xilkernel) and everything works fine. To transmit the data I use RTP protocol and the

three functions: int socket(), int bind() and int sendto(). Every of these functions return -1 if any error.

But thats not this case. Function sendto() returns the bytes actually sent and in this case it matches the theoretical value.

 

My application is derived from XAPP915 Reference System: Streaming an MP3 File using RTP.

http://www.xilinx.com/support/documentation/application_notes/xapp915.pdf. In this application there is

no problem with any cache. My application should send wav file but the rest is very similar. I changed only one 

important thing - the copying data from DDR SDRAM to rtp_packet from

 

memcpy(rtp_struct_pointer->mp3_bundle,  start_addr_orig_byte0, bundle_sz+1);

 

to

 

for(i=0; i<samples; i=i+4){
        rtp_struct_pointer->wav_bundle[i] = *start_addr_orig_byte1;
        rtp_struct_pointer->wav_bundle[i + 1] = *start_addr_orig_byte0;
        rtp_struct_pointer->wav_bundle[i + 2] = *start_addr_orig_byte3;
        rtp_struct_pointer->wav_bundle[i + 3] = *start_addr_orig_byte2;
       
        start_addr_orig_byte0 = start_addr_orig_byte0 + 4;   
        start_addr_orig_byte1 = start_addr_orig_byte1 + 4;
        start_addr_orig_byte2 = start_addr_orig_byte2 + 4;
        start_addr_orig_byte3 = start_addr_orig_byte3 + 4;
    }

 

But why it should be a problem.

Another thing which I´m thinking about is the timing of sending of packets. But I´m using

a hardware timer and the timer is not affected by caching.

Or should I use flush or invalidate cache functions?

 

So if you have any idea where the problem could be please write answer. I would be very thankful.

Thanks. Bye


 

Tags (4)
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11 Replies
Explorer
Explorer
17,444 Views
Registered: ‎01-25-2008

Re: Cache and DDR SDRAM

Hi,

 

I use the same device (V4FX12SF363), and I have exactly the same problem.

 

When I enable caches using XCache_Enable...(...) the application exhibits strange behaviour, either the board will not boot, or works on random occasions, without the caches on everything works fine.

 

I have two problems related to the XCache_Enable Function.

 

1.  What is the exact addresses that are required to be passed into the cache enable function.  

2.  How does the cache activation relate to the 'tick boxes' for which memories need to be chached in XPS  (System Assembly View -> Addresses -> ICache & DCache).

 

 

I contacted our FAE and he was unable to provide an exact answer, other than to look through the source code for the XCache_Enable functions.

 

Could someone from Xilinx please provide some more information on the XCache_Enable function?

 

Thanks

Lachlan.

 

Lachlan Grogan
CEO, SIL3 Pty Ltd
Melbourne, Australia
http://sil3.com.au
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Visitor 0004231010
Visitor
17,430 Views
Registered: ‎04-07-2009

Re: Cache and DDR SDRAM

Hello,

I think that maybe I can help you.

 

1.  What is the exact addresses that are required to be passed into the cache enable function.  

 

void XCache_EnableDCache(unsigned int regions);

void XCache_EnableICache(unsigned int regions);

 

Both functions behave the same way. You need to give them information which regions are cachable.

 

http://www.xilinx.com/ise/embedded/edk91i_docs/standalone_v1_00_a.pdf:

 

Each bit in the regions parameter represents 128 MB of memory. A value of 0x80000000 enables

the data cache for the first 128 MB of memory (0 - 0x7FFFFFF). A value of 0x1 enables the data cache

for the last 128 MB of memory (0xF8000000 - 0xFFFFFFFF).

 

So like I wrote I´m using DDR SDRAM which is mapped -> DDR SDRAM 0x00000000 - 0x03ffffff. So if

I want to enable caching for this memory I need to pass 0x80000000 to the enable functions. It will allow caching

for bigger address range (0x00000000 - 0x07ffffff) (there is no way how to specify smaller ranges),

but I know that the range 0x03ffffff - 0x07ffffff is free - there is no component mapped. The "nearest" component starts

from 0x40000000.

 

If I want to use cache for BRAM which is mapped -> BRAM 0xffff0000 - 0xffffffff, I´ll have to pass 0x00000001 to the

enable functions. This will allow caching for 0xf8000000 - 0xffffffff. The situation is the same, the address range allow for caching

is bigger then I need but in this bigger address range there is no other component mapped.

 

Together I´ll pass to both enable functions 0x80000001.

 

2.  How does the cache activation relate to the 'tick boxes' for which memories need to be chached in XPS  (System Assembly View -> Addresses -> ICache & DCache).

 

If you want to enalbe caching for a specific memory, you will have to do two things. You will have to tick the boxes you specified (or in BSB

you will have to allow caching and than specify for which memories you want to do it) (I don´t know but may be it´s something like hardware enablement). Then you´ll have to allow the cache in software by the two functions which we talk about in question number one.


I also think that they could specify the cache functions better. But I´m really not able to understand the:

 

void XCache_FlushDCacheLine(unsigned int adr);

void XCache_InvalidateDCacheLine(unsigned int adr);.

 

I don´t know how to operate with adr parameter. Is anybody capable to write some more explanation of how

I should use these two functions? If someone provide a sample C code I would be very happy.

 

Thanks

 

 

Explorer
Explorer
17,421 Views
Registered: ‎01-25-2008

Re: Cache and DDR SDRAM

Hi,

 

Thanks for your very concise explanation.

 

I have tried this approach too and had unreliable results.  I only have 64Mb of data in my system and enabled the first region (0x80000000).  By setting 0x01 you may actually be chaching your BRAM and bootloader which is a bit uselss.

 

The secrets to the success rely in the Cache Flush routines I think.  

 

The PPC405 core has inbuilt caches and I would assume they are invalidated at reset, but I can't be sure?

Can a Xilinx expert help us?

 

Some code examples would be great!

 

Thanks

Lachlan.

 

 

Lachlan Grogan
CEO, SIL3 Pty Ltd
Melbourne, Australia
http://sil3.com.au
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Explorer
Explorer
17,402 Views
Registered: ‎08-29-2008

Re: Cache and DDR SDRAM

Hi guys,

 

Somebody wrote:

>When I enable caches using XCache_Enable...(...) the application exhibits strange behaviour, either the board will not boot, or works on random occasions, without the caches on everything works fine.

 

What does it mean: the board will not boot!!!

The cache functionality is enabled at the beginning of the main method! The OS (xilkernel/standalone) does execute a lot of things before that...

Are you able to specify exactly what you mean with "strange behaviour" (data lost, program execution, ...)?

 

Be carefull with data exchange using cache functionality! The PPC as sender has to ensure that the data chunk through the cache must be written into the DDR SDRAM by flushing the data cache!

 

First I would try out the following scenarios:

1/ enable only the instruction cache

2/ enable both caches and move your memory area concerning data exchange to the ethernet controller outside the data cache region by the MMU (physica2virtual address space)

 

Rgds,

Kai

 

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Visitor 0004231010
Visitor
17,395 Views
Registered: ‎04-07-2009

Re: Cache and DDR SDRAM

Thank you for your answers.

 

I work on my application and discoverd this.

 

The program runs well when I  enable data cache or instruction cache only (for SDRAM):

 

XCache_EnableICache(0x00000000);
XCache_EnableDCache(0x80000000);

 

or

 

XCache_EnableICache(0x80000000);
XCache_EnableDCache(0x00000000);.

 

Both examples work well. But when I enable data cache and instruction cache for SDRAM at the same

time, program doesn´t work. My code and data are too big for BRAM so I store everything in SDRAM.

 

However previous versions of my program have smaller code and I´m able to use a BRAM for it. So

I tell the linker to place my code in BRAM (.text) and everything else to place in SDRAM and the program works

again even if I enable data and instruction code for SDRAM at the same time.

 

So this:

 

XCache_EnableICache(0x80000000);
XCache_EnableDCache(0x80000000);

 

works fine when I split the code and data (but I need to store everything in SDRAM). That seems

logical because I enable instruction caching for SDRAM but in SDRAM aren´t any instructions

anymore.

 

Then if I leave code and data splitted in separate memories and enable caching even for BRAM

(you might be right that is useless but it could tell us something useful) it doesn´t work. It means:

 

XCache_EnableICache(0x80000001);
XCache_EnableDCache(0x80000001);

 

not works. So does it mean that I cannot use caching for data and instructions at the same time? Regardless

where I store the instructions and data? But I know that the reference design works well with data and instructions caching

at the same time (with .text and data stored in SDRAM).

 

Thank you dorau for your opinions. I have already tested your first advice.

I must admit that I know absolutly nothing about virtual addressing. But I will look at it. However I have another questions.

 

You wrote:

 

Be carefull with data exchange using cache functionality! The PPC as sender has to ensure that the data chunk through the cache must be written into the DDR SDRAM by flushing the data cache!

 

But I´m not writing to SDRAM anything, I´m reading from SDRAM. So that is not the problem? Or it is?

 

2/ enable both caches and move your memory area concerning data exchange to the ethernet controller outside the data cache region by the MMU (physica2virtual address space)

 

By memory area concerning data exchange you mean address range of SDRAM where I store audio data? But that´s

a big area -> 0x01000000 - 0x02ffffff. Also the reference design didn´t use virtual addresses.

 

Thanks for any answer.
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Explorer
Explorer
17,377 Views
Registered: ‎08-29-2008

Re: Cache and DDR SDRAM

Hi 0004231010,

 

>By memory area concerning data exchange you mean address range of SDRAM where I store audio data? But that´s

>a big area -> 0x01000000 - 0x02ffffff. Also the reference design didn´t use virtual addresses.

 

That is my issue! I guess you would like to move audio data to the ethernet controller in the following way:

PPC writes audio data to the DDR SDRAM, after that the ethernet controller as DMA master reads the audio data

from the DDR SDRAM and send them to the network.

The Problem: audio data which have not been written into the DDR SDRAM completely (one or more chunks remain(s) in data cache)

You enables the first data cache region (256M: 0x00000000...0x0ffffff) and your area for the audio data is 0x01000000 - 0x02ffffff.

The data cache covers up your audio data area in DDR SDRAM!!!

 

You told us that the reference design works well with enabling instruction AND data cache! This issue sounds unbelievable ;-(

 I also assume an invalid data pointer in your source code?!?! Enable the MMU and the PPC will be interrupted by invalid pointer access!

 

Rgds,

Kai

 

Ps: I remember that enabling data and instruction cache worked very well in past projects. So I do not assume a xilkernel/standalone OS cache library problem...

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Visitor 0004231010
Visitor
17,368 Views
Registered: ‎04-07-2009

Re: Cache and DDR SDRAM

Hi,

thank you for your sugestions.

 

The reference design work because the audio samples are load to SDRAM by command dow -data <audio_file>.mp3 0x01000000. The samples

are not received during the program execution. That will be the next step. Even in my program I already start with the samples in memory.

 

I think that MMU is enabled whole time. In PPC405 features (configure IP ...) is ticked off - Enable the Memory-management unit (MMU). It relates to C_MMU_ENABLE HDL parameter.

 

In http://www.xilinx.com/support/documentation/sw_manuals/edk10_oslib_rm.pdf on page 108 (chapter memory protection) I found:

 

Note: Full virtual memory management is not supported by Xilkernel. Even when a full MMU is available
on MicroBlaze, only transparent memory translations are used, and there is no concept of demand
paging.
Note: Xilkernel does not support the same set of features using the MMU on PowerPC processors.

 

Could the problem be in wrong protection of memory segments?

 

I tested the program more and I discovered following:

 

If only data or instruction cache is allowed program works and I´m sending rtp packets correctly. I receive them using Ethereal. I ticked off the option enable transport name resolution and the program realizes and receives udp packets and that´s right becouse I use udp protocol (transport layer) to send rtp packets (application layer).

 

But when I enable both caches program doesn´t work correctly. Ethereal receives packets but name them as Fragmented IP protocol (proto=UDP 0x11, off=0)

 

On some forum about ethereal I found this:

 

Note that if

    1) you didn't capture the full packet (i.e., you gave a snapshot
       length not large enough to get all the packet data)

or

    2) the IP checksum isn't valid

reassembly isn't done.
(It means that it´s not possible to extract udp packet from ip packet.)

 

So it means that I´m not sending full packets? How is it related to my cache problem? I´m using hardware

timer to measure time between sending of packets so there cannot be a problem. I think.

 

Also it seems that the number of packets send is much smaller.

 

Any suggestions? Please help. 

Thanks

 

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Explorer
Explorer
17,341 Views
Registered: ‎01-25-2008

Re: Cache and DDR SDRAM

Hi Everyone,

 

I just did a ModelSIM of my basic system to test the cache issue.  In the ModelSIM log I found the following item:

 

 

# ** Note (SmartModel): # *=========================================================================* # * WARNING! The core model is forcing the internal data caches invalid in * # * in order to save simulation cycles. This won't work on real hardware! * # * Your software is responsible for invalidating the caches before caching * # * is turned on. * # *=========================================================================* # >> Forcing Reset of D-CACHE Tags << # >> Forcing Reset of D-CACHE LRU/DIRTY << # >> Forcing Reset of I-CACHE LRU/Valid <<

 

Hence I think in a standalone system you will need to invalidate each cache line before enabling the caches!..  This is a step that I have missed in my application, but I assume that XilinxKernel does this correctly..

 

Regards

Lachlan.

 

 

 

Lachlan Grogan
CEO, SIL3 Pty Ltd
Melbourne, Australia
http://sil3.com.au
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Visitor 0004231010
Visitor
17,331 Views
Registered: ‎04-07-2009

Re: Cache and DDR SDRAM

Hello,

 

I found what was "wrong" with my application. I was thinking what is the difference

between my application and the reference application. As I said I´m sending rtp packets.

They should be about 3540 bytes long and they are if only one cache is activated. But if I activate

both caches Ethereal indicates that the packets are not complete and only about 1500 bytes long.

The reference design uses packets about 1300 bytes. And that´s it. If I use packets smaller than

1500 bytes everything goes well even with two caches activated.

 

I don´t know how to explaine it. Maybe some memory options in lwip library are set wrong (too small)?

But why it depends on caches?

 

If anybody has an idea it whould be great if he shares it.

 

Now I have the problem which was here discussed. My design does:

I speak -> audio samples are collected -> send -> on PC received.

But on PC I here an echo. So I think I need to flush data cache. Am I

right?

 

Could someone possibly write how could I do it?

 

I only found (at http://www.xilinx.com/ise/embedded/edk91i_docs/standalone_v1_00_a.pdf):

 

void XCache_FlushDCacheLine(unsigned int adr);


The XCache_FlushDCacheLine( ) function flushes and invalidates the data cache line that
contains the address specified by the adr parameter. A subsequent data access to this address
results in a cache miss and a cache line refill.

 

I´m not sure how to operate with the function. Can anybody write a sample code or give a hint?

 

Thanks

 

 

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Visitor svizzusi
Visitor
4,676 Views
Registered: ‎05-21-2009

Re: Cache and DDR SDRAM

The reference design sent less than 1500 bytes to avoid possible fragmentation issues. Perhaps your packets were getting fragmented since they were exceeding the network MTU. There is a note in the app note on this:

 

"Note: Three MP3 frames are used per RTP packet to obtain the largest possible packets without
fragmentation. Three MP3 frames per RTP packet is less than the de facto 1500 byte MTU. Using three
MP3 frames per RTP packet results in much higher performance than using a single MP3 frame per
packet. Bundling more than three MP3 frames can result in fragmentation, which can have a detrimental
effect on performance."

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Newbie minhtien
Newbie
3,493 Views
Registered: ‎07-12-2008

Re: Cache and DDR SDRAM

Hi you!

Now i have a RTP video streaming project. I found on the internet that XAPP915 is related to RTP. But i can not download XAPP915.ZIP from xilinx any more. If you have this once, could you send it for me or tell me the way to get it? Thanks in advanced!

My email is minhtien711@gmail.com. You can contact with my through this email

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