07-11-2009 10:36 AM
I am using EDK10.1.3 to build a microblaze project, my hardware platform including SPARTAN-3E and SDRAM, but MPMC and SDRAM do not work correctly.
I want to watch if there are any problem with the signals between MPMC and SDRAM, but I can't see DQ_O, DQ_I, DQ_T in port list. And chipsocpe can't watch IO signals directly.
How can I watch these signals???
07-12-2009 09:03 PM
Thank you very much, I'am sure I can't watch data-bus directly with chipscope, but like other IP core, there are bi-directional signals and splitted signals before output to IOB. For example, data-bus is splitted into DATA_O ,DATA_I, DATA_T. I wonder how I can use these splitted signals in chipscope.
My problem is data can't write to SDRAM, and data readed from any address is a constant.
07-12-2009 09:57 PM
Chipscope lists the data_I and data_O signals also along with the data_IO of SDRAM. You can scroll down and select those signals instead of data_IO.
07-12-2009 10:21 PM
07-13-2009 02:53 AM
Thank you very much, I will test your method, but why not display these signals in EDK's ILA, I think not only me who need to debug bi-directional signal in EDK with ICON and ILA .
07-13-2009 10:07 PM
The term "debug bidirectional signal" may be misleading to some. The only bidirectional signal is the signal external to the IOBUF. Still, it could be useful to see the input, output, and tristate control of the buffer...
Have you considered using the ngcbuild approach:
http://forums.xilinx.com/xlnx/board/message?board.id=EDK&message.id=2795 (Using ChipScope to look at my custom IP core's internals)
This has proven to be useful in a number of scenarios...
07-14-2009 06:51 AM - edited 07-14-2009 06:52 AM
The signal names going in and out of the IOB may not be what you think they are for a variety of reasons.
I know you aren't... The custom IP core was just a thread that documents its usage and some of the issues. The process should be the same in both cases (that one and yours) because of details on how parts of the flow are handled.
I would recommend opening an existing implemented design in FPGA editor to verify the net names of the signals doing in and out of the data bus IOBs.
You'll also have to keep in mind which clock domain generated these signals (which you can also confirm here) to make sure that you are using the appropriate clock for the ILA. But the first step is to find the names.
07-14-2009 09:48 PM
Thank you very much, I'll try your method.
And I also encountered anther problem: when I add some signal of external port(for example,DQM of MPMC in EDK10.1.3) into ILA in EDK or chipscope core inserter, during implementing, it reported: output pad net ...... has an illegal load: pin D on block ...... type FDP.
It seemed that the I/OBUF caused this problem, right? And how to solve?