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gunnerone
Observer
Observer
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Registered: ‎03-12-2013

Can't edit connected ports in EDK and quad SPI config

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Hi,

I have two problems I've come across in getting my project working.  In EDK when I go to the "System Assembly View", and to the "Ports" tab, if I click on any of the entries in the "Connected Port" column I can't seem to modify them.  It shows a little red pencil on the right side of this column, and I can change the Direction, Range, Class, etc.  However, when I click on the Connected Port column the red pencil dissapears for that column but there's no drop down, and I can't type anything in.  If I open the mhs file directly I can make changes there that then show up in the System Assembly View, but I can't seem to edit them from the GUI.  I have Platform Studio version 14.4.

 

 

The second problem I've run into is in getting an axi_quad_spi device to work.  I just want to use it with an A2D.  I have it configured like so:

SCK Ratio: 4 (I have the 100Mhz clock connected to it, and need 25Mhz for the A2D)

SPI Mode: Standard SPI Mode

AXI Interface Type: AXI4 Full Interface

XIP Mode: Non XIP Mode

 

I have the SPISEL port connected to net_vcc.

When I try to Synthesize or run Design Rule Checks it comes back with:

ERROR:EDK:3900 - issued from TCL procedure "::hw_axi_quad_spi_v2_00_a::check_iplevel_ports" line 20
axi_quad_spi_0 (axi_quad_spi) - Only allowed value for C_SCK_RATIO is 2 when the core is configured on AXI4 Memory Mapped Interface.

 

What am I doing wrong?  I need the ratio of 4 to get the 25MHz clock.

Thanks

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gunnerone
Observer
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Registered: ‎03-12-2013

In-case anyone else has the problem with not being able to edit the connected ports in the EDK I've found the solution.  When you're on the "System Assembly View" under the "Ports" tab you need to right click on one of the row headers (Name, Connected Port, etc.), and make sure the "Net" field is checked.  It's actually the "Net" column that needs to be modified to create the connections and not the "Connected Port" field.

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gunnerone
Observer
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Registered: ‎03-12-2013

In-case anyone else has the problem with not being able to edit the connected ports in the EDK I've found the solution.  When you're on the "System Assembly View" under the "Ports" tab you need to right click on one of the row headers (Name, Connected Port, etc.), and make sure the "Net" field is checked.  It's actually the "Net" column that needs to be modified to create the connections and not the "Connected Port" field.

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elvisjohndowson
Explorer
Explorer
5,367 Views
Registered: ‎12-30-2008

I ran into the same problem. I noticed that if I re-size the XPS window so that it's wider, the pop-up window for specifying the connections will appear. For some reason, it remembers the window width and gets stuck to the far right of the window.

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mstamler3037
Contributor
Contributor
5,305 Views
Registered: ‎08-30-2011

I have discovered that if the screen resolution is lower than HD then the edit port fields do not appear at all. I am using a two-screen system with one screen at 800x600. There it does not appear. But when I move XPS to the higher full HD of my laptop then it does appear.

 

wmaguire
Explorer
Explorer
5,096 Views
Registered: ‎06-21-2013

Yes, thanks for the post, 

 

I spent nearly 1/2 a day trying to locate this one.  I want to use Vivado for my IP integration but the company I work for is making me use this XPS, PlanAhead stuff.  My impression of the software so far is that it is terrible, quirky and buggy.  

 

I don't think Xilinx could have made it more ilogical if they had tried.

 

Regards

 

 

Walter

 

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Anonymous
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@gunnerone wrote:
The second problem I've run into is in getting an axi_quad_spi device to work.  I just want to use it with an A2D.  I have it configured like so:

SCK Ratio: 4 (I have the 100Mhz clock connected to it, and need 25Mhz for the A2D)

SPI Mode: Standard SPI Mode

AXI Interface Type: AXI4 Full Interface

XIP Mode: Non XIP Mode

 

I have the SPISEL port connected to net_vcc.

When I try to Synthesize or run Design Rule Checks it comes back with:

ERROR:EDK:3900 - issued from TCL procedure "::hw_axi_quad_spi_v2_00_a::check_iplevel_ports" line 20
axi_quad_spi_0 (axi_quad_spi) - Only allowed value for C_SCK_RATIO is 2 when the core is configured on AXI4 Memory Mapped Interface.

 

What am I doing wrong?  I need the ratio of 4 to get the 25MHz clock.

Thanks


Regarding this issue, you'll need to either connect a slower clock to EXT_SPI_CLK so that you can use a ratio of 2, or you'll have to use the AXI4lite interface instead of the AXI4 interface.  (The only difference between the two as far as I know is that the lite interface doesn't support burst reads, so it'd be marginally slower -- but then I never worked out the proper way to make software generate a burst read at a single register address anyway.)

 

Use a clock_generator (or the Clock Wizard) to generate a 50 MHz clock from your standard clock.

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