I have been trying to use the Hard TEMAC core with my Virtex 4 FX 12 development platform (Avnet FX12 Eval Board), but without any luck... When I start a new design I have the possibility to use either the opb_ethernet, opb_ethernetlite or the plb_ethernet but not the plb_temac and hard_temac cores which I want to use because they are already in the fabric and payed for...
So I start the design and add the plb_temac and hard_temac cores, connect the plb_temac to the plb bus and set the address. Then I connect he hard_temac to the plb_temac,go to the "Software Platform Setting" and check XILKERNEL and IWIP.
But then, when I try to generate the bitstream I get the following error:
C:\EDK\hw\XilinxProcessorIPLib\pcores\hard_temac_v3_00_b\data\hard_temac_v2_1 _0.mpd line 98 - connection is not connected to an external port! MPD subproperties IOB_STATE=BUF|REG require that the input port be connected directly to an external port.
What am I missing?... I should connect the core to the external ports, but how?
Check your MHS file to see what pin you didn't connect along with UCF file. You need to click and make sure every pin(For the standard you are using) is external even if it is external. Just do it please click on each pin used in phy standard and make external tool will say that it is insanity check.
Are you running RGMII make sure you connect RGMII_RXC_0.
If you are running GMII you need to connect the TX clock pin to MII_TX_CLK_0
And GMII_TX_CLK_0 to phy 125Mhz clock
If ISE is your top level make sure you don't add any IBUFG to the input ports to EDK.
Also start off with a good design go download and example design from AVNET. Even for custom boards I never and I mean never start fresh to many settings in EDK and you will spend weeks debugging.