07-03-2009 06:56 AM
07-03-2009 03:59 PM
couldnt understand your point completely. but if u r looking for ucf constraints regarding ddr2 of ur board. u can get those constraints from the following directory in ur pc.
<xilinx installation directory>\EDK\board\Xilinx\boards
07-03-2009 09:41 PM
This is for version 10.1 Service pack 3.
If the DDR2 design is exactly the same as in ML505 then you can use the constraints in the file DDR2_SDRAM_MPMC mentioned in <drive>:\Xilinx\10.1\EDK\board\Xilinx\boards\Xilinx_ML505\data
But if you want to move some pins which will not be as same as in ML505 then what you do is you complete your design then give the new UCF to MIG for it to verify and if that is successful then you can use the design in your board.
07-03-2009 11:32 PM
07-06-2009 10:10 AM
Hello. Thanks for all your replies - things are getting slightly clearer now. I have now upraded the tools to ISE/EDK 11.2 (MIG V3.1). I have used the MIG to generate a design targetted to the ML505. I have modified the resulting UCF with the new pin locations with the intention of feeding this back into the MIG to generate a new, modified design. I have used the "verify ucf" function in the MIG to check my new version and have cleared up most of the issues (DQ/DM/DQS for each byte grouped together in the same bank, CC pins for DQS, etc.) apart from this one:
ERROR: ddr2_ck(Clock) should not be allocated to bank 21.
ERROR: ddr2_ck_n(Clock) should not be allocated to bank 21.
ERROR: ddr2_ck(Clock) should not be allocated to bank 17.
ERROR: ddr2_ck_n(Clock) should not be allocated to bank 17.
Net ddr2_ck LOC=AK29; # Bank 21 (xc5vlx50t-ff1136)
Net ddr2_ck LOC=W24; # Bank 17
Net ddr2_ck_n LOC=AJ29; # Bank 21
Net ddr2_ck_n LOC=V24; # Bank17
My 32b data bus is in banks 21 (dq[15..0]) and 17 (dq[31..0]), address and control bits are in bank 15.
Can anyone tell me what rule I'm breaking with the clock placement?
07-06-2009 10:51 AM
07-06-2009 11:53 PM - edited 07-07-2009 12:51 AM
I have tried moving the clocks (x2 pairs) to bank 15 (addr/control) and the MIG verify process now passes error free. The original Xilinx ML505 design has the ddr2 clocks mixed in with the data lines (banks 17 and 21) - how did they get this past the MIG??!!
07-07-2009 08:24 AM