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grahamhowell
Visitor
Visitor
7,324 Views
Registered: ‎09-17-2008

Changing DDR2 pin locations and constraints on Virtex-5 reference board.

Hello.

We are in the process of producing a design based upon the Virtex-5 ML505 dev. board.  The PCB layout people want to move some of the DDR2 pins. The firmware was produced using Base System Builder (ISE/EDK 10.1 SP3).  I'm struggling to work out exactly how to generate the DDR-related constraints needed to update the UCF - I can manage the pin LOCs but there are many others which were generated by (I think) MIG (V2.3).  Can anyone help me with the process I need to follow or point me in the direction of a step by step idiot's guide?

Thanks,

Graham.
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8 Replies
wasiqnaeem
Participant
Participant
7,314 Views
Registered: ‎06-11-2009

i

couldnt understand your point completely. but if u r looking for ucf constraints regarding ddr2 of ur board. u can get those constraints from the following directory in ur pc.

 

<xilinx installation directory>\EDK\board\Xilinx\boards

 

regards

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prateek_bhatt
Scholar
Scholar
7,309 Views
Registered: ‎08-21-2008

Hello.

This is for version 10.1 Service pack 3. 

If the DDR2 design is exactly the same as in ML505 then you can use the constraints in the file DDR2_SDRAM_MPMC mentioned in <drive>:\Xilinx\10.1\EDK\board\Xilinx\boards\Xilinx_ML505\data 

But if you want to move some pins which will not be as same as in ML505 then what you do is you complete your design then give the new UCF to MIG for it to verify and if that is successful then you can use the design in your board.  

Best of luck.
--
Unlimited in my Limits.
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vsiva
Xilinx Employee
Xilinx Employee
7,303 Views
Registered: ‎01-18-2008

graham - Getting memory controller constraints correctly for a custom board is not trivial if you aren't exactly copying the schematics of an existing board. I would suggest that you file a hotline case, or talk to your FAE and get proper support *before* you hand it over the PCB layout people. At a high level, you start with MIG from coregen, and ask it to suggest optimal locations and constraints. That is a lot easier than getting your design retrofitted to MIG.
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grahamhowell
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Visitor
7,277 Views
Registered: ‎09-17-2008

Hello.  Thanks for all your replies - things are getting slightly clearer now.  I have now upraded the tools to ISE/EDK 11.2 (MIG V3.1).  I have used the MIG to generate a design targetted to the ML505.  I have modified the resulting UCF with the new pin locations with the intention of feeding this back into the MIG to generate a new, modified design.   I have used the "verify ucf" function in the MIG to check my new version and have cleared up most of the issues (DQ/DM/DQS for each byte grouped together in the same bank, CC pins for DQS, etc.) apart from this one:

 

ERROR: ddr2_ck[0](Clock) should not be allocated to bank 21.
ERROR: ddr2_ck_n[0](Clock) should not be allocated to bank 21.
ERROR: ddr2_ck[1](Clock) should not be allocated to bank 17.
ERROR: ddr2_ck_n[1](Clock) should not be allocated to bank 17.

 

 

Net ddr2_ck[0] LOC=AK29;   # Bank 21  (xc5vlx50t-ff1136)

Net ddr2_ck[1] LOC=W24;      # Bank 17

Net ddr2_ck_n[0] LOC=AJ29;  # Bank 21
Net ddr2_ck_n[1] LOC=V24;   # Bank17

 

My 32b data bus is in banks 21 (dq[15..0]) and 17 (dq[31..0]), address and control bits are in bank 15.

 

Can anyone tell me what rule I'm breaking with the clock placement?

 

Thanks,

Graham.

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jschmitz
Xilinx Employee
Xilinx Employee
7,275 Views
Registered: ‎10-23-2007

I suspect that MIG wants ddr2_ck to be in the same bank as the address/control.  Can you put it in bank 15 and run the Verify UCF?  I think this is done to minimize the skew.
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grahamhowell
Visitor
Visitor
7,258 Views
Registered: ‎09-17-2008

Hello.

I have tried moving the clocks (x2 pairs) to bank 15 (addr/control) and the MIG verify process now passes error free.  The original Xilinx ML505 design has the ddr2 clocks mixed in with the data lines (banks 17 and 21) - how did they get this past the MIG??!!

Graham. 

Message Edited by grahamhowell on 07-07-2009 12:51 AM
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jschmitz
Xilinx Employee
Xilinx Employee
7,234 Views
Registered: ‎10-23-2007

I suspect that there are two reasons for this: one is that MIG is being too agressive in Verify UCF and this may only need to be a warning or suggestion for minimizing skew, and two is that the ML505 was likely designed (or in design) before the MIG rules were finalized.  I think #1 is the main reason.
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Anonymous
Not applicable
7,143 Views

Hi,

 

Did you deselect the PPC440 checkbox in your MIG design to modify pin locations?

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