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Adventurer
Adventurer
3,694 Views
Registered: ‎08-23-2012

Checksum Offloading on Zynq, Vivado, SDK 2014.1

According to UG585 Technical Reference the Gigabi Ethernetcontroller can be programmed to perform IP, TCP and UDP checksum offloading in both receive and transmit directions.

 

When activating

 PARAMETER TCP_IP_RX_CHECKSUM_OFFLOAD = true
 PARAMETER TCP_IP_TX_CHECKSUM_OFFLOAD = true

in lwip settings the sw (xapp1026 for example) crashes.

 

How can I activate these options in Vivado/SDK 2014.1 ??

 

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3 Replies
Xilinx Employee
Xilinx Employee
3,691 Views
Registered: ‎08-02-2007

Re: Checksum Offloading on Zynq, Vivado, SDK 2014.1

Hi,

 

Updating the MSS should be sufficient. I have looked at the MLD of LWIP provided in 2014.1 and it looks that these parameters

are indeed there. Refer to the snapshot attached.

 

Would that be possible to create a new BSP with LWIP being used rather than updating the one provided by XAPP1026?

 

--Hem

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Adventurer
Adventurer
3,686 Views
Registered: ‎08-23-2012

Re: Checksum Offloading on Zynq, Vivado, SDK 2014.1

I created a new BSP. I use the sw of xapp1026 v3.2 only (and a copy of the settings for lwip for Zynq)

 

Your screeshot shows a remark "Applicable only for AXI-Ethernet".

 

Does this mean a TEMAC in the PL?

 

 

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Xilinx Employee
Xilinx Employee
3,669 Views
Registered: ‎08-02-2007

Re: Checksum Offloading on Zynq, Vivado, SDK 2014.1

Hi,

 

Yes that is correct understanding. Refer to the snapshot given here.

 

It looks GigE this parameter is always present, so it is not needed to be applied again.

 

--Hem

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