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Visitor stone9502
Registered: ‎07-31-2009

Chipscope PLB46 IBA and DDR access problem

Dear all,


I met a problem when using chipscope PLB46 iba.


In my design, I have one microlbaze processor, one PLB46 bus, several PLB46 slaves like XPS Timer, MPMC DDR controller. Before I add the chipscope plb46 iba, the system works fine, my code run on microlbaze can access DDR correctly.


But after I add the chipscope plb46 iba, if I check all the observe options in the plb46 iba (monitor all the PLB46 signals), the DDR access will fail (write one data and read the same location but the data is not correct), while the access to xps timer is still correct.


If I don't check the options related to the PLB46 master signlas, (i.e,  don't check the options in the last 3 rows in the chipscope plb46 iba), it seems the DDR access becomes correct again.


I am not sure where the bug comes from.  2 possibility:


1: from chipscope plb46 iba.

pro: without this IBA, the system wroks well.

con: other PLB slaves work well


2: from DDR

pro: after insert the IBA, only the DDR access is not correct, other PLB slaves work well.

con: DDR works well without IBA



Any idea?






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Visitor stone9502
Registered: ‎07-31-2009

Re: Chipscope PLB46 IBA and DDR access problem

I was wondering whether that's because the IPLB and DPLB in microblaze is only regarded as one master, so that master related signal like arbitration is optimised ?
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