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Visitor azarias
Visitor
7,941 Views
Registered: ‎09-28-2007

Chipscope XPS 9.1 issues

Hi!
I have a fairly complex design in a Virtex2pro board. I use Xilinx Platform Studio EDK 9.1i. I need to check some signals in the fpga and I wanted to use chipscope pro 9.1. I import the devices:
* chipscope_ila
* chipscope_icon

I established the connections and I started resynthesizing. However really soon I get this long, and for be uncomprensible message, I copied it right after the synthesis without the debug modules.
Anybody knows how I can fix it?
Thanks,
~Andrea




Reading arguments from file C:/Projects/Crashtest/Leon_withPPC_minimal_gtech_big_gates_1_fault_dynamic-tracebuffer-1_run/implementation/cs_coregen_chipscope_ila_0.arg
Warning: Arguments from file will override command line arguments

Creating EDIF NetlistC:\Projects\Crashtest\Leon_withPPC_minimal_gtech_big_gates_1_fault_dynamic-tracebuffer-1_run/implementation/chipscope_ila_0_wrapper/\cs_coregen_chipscope_ila_0.edn
Component Name: cs_coregen_chipscope_ila_0
Manufacturer ID: 1
Core Type: 2
Core Version: v9.1.2
Device Family: Virtex2P
SRL16 Type: SRLC16/E
RAM Type: 16384-bit block RAM
Clock Edge Used for Sampling: rising edge
RPM Usage: enabled
Trigger Output Port: enabled
Storage Qualification: enabled
Data Same as Trigger: true
  Data port is made up of the following trigger ports:
    Trigger Port 0
    Trigger Port 1
    Trigger Port 2
    Trigger Port 3
Aggregate Data Width: 130
Data Depth: 512
Enable Gap Recording: false
Enable Timestamp Recording: false
Number of Trigger Ports: 4
  Trigger Port 0 Width:1
  Trigger Port 1 Width:64
  Trigger Port 2 Width:1
  Trigger Port 3 Width:64
Number of Match Units: 4
  Match Unit 0 Info:
    Connection: Trigger Port 0
    Type: Basic
    Match Counter : disabled
  Match Unit 1 Info:
    Connection: Trigger Port 1
    Type: Basic
    Match Counter : disabled
  Match Unit 2 Info:
    Connection: Trigger Port 2
    Type: Basic
    Match Counter : disabled
  Match Unit 3 Info:
    Connection: Trigger Port 3
    Type: Basic
    Match Counter : disabled
Trigger Sequencer Type : Basic
  Number of trigger sequencer levels: 16
External capture : disabled
Force RPM Grid Usage: no
Resource Utilization Estimate   LUT:427    FF:607    BRAM:5

Warning: EDIF Netlist being generated

Post Processing EDIF netlist C:\Projects\Crashtest\Leon_withPPC_minimal_gtech_big_gates_1_fault_dynamic-tracebuffer-1_run/implementation/chipscope_ila_0_wrapper/\cs_coregen_chipscope_ila_0.edn

Generating constraints file C:\Projects\Crashtest\Leon_withPPC_minimal_gtech_big_gates_1_fault_dynamic-tracebuffer-1_run\implementation\chipscope_ila_0_wrapper\cs_coregen_chipscope_ila_0.ncf

Generating CDC file C:\Projects\Crashtest\Leon_withPPC_minimal_gtech_big_gates_1_fault_dynamic-tracebuffer-1_run\implementation\chipscope_ila_0_wrapper\cs_coregen_chipscope_ila_0.cdc
-----------------------------------------------
**********************************************
Running XST for Chipscope-EDK Port Mapper core
**********************************************
-----------------------------------------------

ERROR:MDT - chipscope_ila_0 (chipscope_ila) - Release 9.1.02i - xst J.30
   Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
   --> -->
   TABLE OF CONTENTS
     1) Synthesis Options Summary
     2) HDL Compilation
     3) Design Hierarchy Analysis
     4) HDL Analysis
     5) HDL Synthesis
        5.1) HDL Synthesis Report
     6) Advanced HDL Synthesis
        6.1) Advanced HDL Synthesis Report
     7) Low Level Synthesis
     8) Partition Report
     9) Final Report
        9.1) Device utilization summary
        9.2) Partition Resource Summary
        9.3) TIMING REPORT


   =========================================================================
   *                      Synthesis Options Summary                        *
   =========================================================================
   ---- Source Parameters
   Input Format                       : MIXED
   Input File Name                    :
   "cs_edk_port_mapper_chipscope_ila_0_xst.prj"

   ---- Target Parameters
   Target Device                      : 2vp30ff896-7
   Output File Name                   :
   "../implementation/chipscope_ila_0_wrapper/chipscope_ila.ngc"

   ---- Source Options
   Top Module Name                    : chipscope_ila

   ---- Target Options
   Add IO Buffers                     : NO

   ---- General Options
   Optimization Goal                  : speed
   Hierarchy Separator                : /

   ---- Other Options
   Cores Search Directories           :
   {../implementation/chipscope_ila_0_wrapper}

   =========================================================================

   WARNING:Xst:29 - Optimization Effort not specified
   The following parameters have been added:
   Optimization Effort                : 1

   =========================================================================

   =========================================================================
   *                          HDL Compilation                              *
   =========================================================================
   Compiling vhdl file
   "C:/Projects/Crashtest/Leon_withPPC_minimal_gtech_big_gates_1_fault_dynamic-t
   racebuffer-1_run/hdl/cs_edk_port_mapper/cs_edk_port_mapper_chipscope_ila_0.vh
   d" in Library chipscope_ila.
   Entity <chipscope_ila> compiled.
   Entity <chipscope_ila> (Architecture <imp>) compiled.

   =========================================================================
   *                     Design Hierarchy Analysis                         *
   =========================================================================
   Analyzing hierarchy for entity <chipscope_ila> in library <chipscope_ila>
   (architecture <imp>) with generics.
       C_DATA_IN_WIDTH = 32
       C_DATA_SAME_AS_TRIGGER = 1
       C_DEVICE = "2vp30"
       C_DISABLE_RPM = 0
       C_ENABLE_TRIGGER_OUT = 1
       C_FAMILY = "virtex2p"
       C_NUM_DATA_SAMPLES = 512
       C_PACKAGE = "ff896"
       C_SPEEDGRADE = "-7"
       C_TRIG0_TRIGGER_IN_WIDTH = 1
       C_TRIG0_UNIT_COUNTER_WIDTH = 0
       C_TRIG0_UNIT_MATCH_TYPE = "basic"
       C_TRIG0_UNITS = 1
       C_TRIG10_TRIGGER_IN_WIDTH = 8
       C_TRIG10_UNIT_COUNTER_WIDTH = 0
       C_TRIG10_UNIT_MATCH_TYPE = "basic"
       C_TRIG10_UNITS = 0
       C_TRIG11_TRIGGER_IN_WIDTH = 8
       C_TRIG11_UNIT_COUNTER_WIDTH = 0
       C_TRIG11_UNIT_MATCH_TYPE = "basic"
       C_TRIG11_UNITS = 0
       C_TRIG12_TRIGGER_IN_WIDTH = 8
       C_TRIG12_UNIT_COUNTER_WIDTH = 0
       C_TRIG12_UNIT_MATCH_TYPE = "basic"
       C_TRIG12_UNITS = 0
       C_TRIG13_TRIGGER_IN_WIDTH = 8
       C_TRIG13_UNIT_COUNTER_WIDTH = 0
       C_TRIG13_UNIT_MATCH_TYPE = "basic"
       C_TRIG13_UNITS = 0
       C_TRIG14_TRIGGER_IN_WIDTH = 8
       C_TRIG14_UNIT_COUNTER_WIDTH = 0
       C_TRIG14_UNIT_MATCH_TYPE = "basic"
       C_TRIG14_UNITS = 0
       C_TRIG15_TRIGGER_IN_WIDTH = 8
       C_TRIG15_UNIT_COUNTER_WIDTH = 0
       C_TRIG15_UNIT_MATCH_TYPE = "basic"
       C_TRIG15_UNITS = 0
       C_TRIG1_TRIGGER_IN_WIDTH = 64
       C_TRIG1_UNIT_COUNTER_WIDTH = 0
       C_TRIG1_UNIT_MATCH_TYPE = "basic"
       C_TRIG1_UNITS = 1
       C_TRIG2_TRIGGER_IN_WIDTH = 1
       C_TRIG2_UNIT_COUNTER_WIDTH = 0
       C_TRIG2_UNIT_MAT
CH_TYPE = "basic"
       C_TRIG2_UNITS = 1
       C_TRIG3_TRIGGER_IN_WIDTH = 64
       C_TRIG3_UNIT_COUNTER_WIDTH = 0
       C_TRIG3_UNIT_MATCH_TYPE = "basic"
       C_TRIG3_UNITS = 1
       C_TRIG4_TRIGGER_IN_WIDTH = 8
       C_TRIG4_UNIT_COUNTER_WIDTH = 0
       C_TRIG4_UNIT_MATCH_TYPE = "basic"
       C_TRIG4_UNITS = 0
       C_TRIG5_TRIGGER_IN_WIDTH = 8
       C_TRIG5_UNIT_COUNTER_WIDTH = 0
       C_TRIG5_UNIT_MATCH_TYPE = "basic"
       C_TRIG5_UNITS = 0
       C_TRIG6_TRIGGER_IN_WIDTH = 8
       C_TRIG6_UNIT_COUNTER_WIDTH = 0
       C_TRIG6_UNIT_MATCH_TYPE = "basic"
       C_TRIG6_UNITS = 0
       C_TRIG7_TRIGGER_IN_WIDTH = 8
       C_TRIG7_UNIT_COUNTER_WIDTH = 0
       C_TRIG7_UNIT_MATCH_TYPE = "basic"
       C_TRIG7_UNITS = 0
       C_TRIG8_TRIGGER_IN_WIDTH = 8
       C_TRIG8_UNIT_COUNTER_WIDTH = 0
       C_TRIG8_UNIT_MATCH_TYPE = "basic"
       C_TRIG8_UNITS = 0
       C_TRIG9_TRIGGER_IN_WIDTH = 8
       C_TRIG9_UNIT_COUNTER_WIDTH = 0
       C_TRIG9_UNIT_MATCH_TYPE = "basic"
       C_TRIG9_UNITS = 0


   =========================================================================
   *                            HDL Analysis                               *
   =========================================================================
   Analyzing generic Entity <chipscope_ila> in library <chipscope_ila>
   (Architecture <imp>).
       C_FAMILY = "virtex2p"
       C_DEVICE = "2vp30"
       C_PACKAGE = "ff896"
       C_SPEEDGRADE = "-7"
       C_NUM_DATA_SAMPLES = 512
       C_DATA_SAME_AS_TRIGGER = 1
       C_DATA_IN_WIDTH = 32
       C_ENABLE_TRIGGER_OUT = 1
       C_DISABLE_RPM = 0
       C_TRIG0_UNITS = 1
       C_TRIG0_TRIGGER_IN_WIDTH = 1
       C_TRIG0_UNIT_COUNTER_WIDTH = 0
       C_TRIG0_UNIT_MATCH_TYPE = "basic"
       C_TRIG1_UNITS = 1
       C_TRIG1_TRIGGER_IN_WIDTH = 64
       C_TRIG1_UNIT_COUNTER_WIDTH = 0
       C_TRIG1_UNIT_MATCH_TYPE = "basic"
       C_TRIG2_UNITS = 1
       C_TRIG2_TRIGGER_IN_WIDTH = 1
       C_TRIG2_UNIT_COUNTER_WIDTH = 0
       C_TRIG2_UNIT_MATCH_TYPE = "basic"
       C_TRIG3_UNITS = 1
       C_TRIG3_TRIGGER_IN_WIDTH = 64
       C_TRIG3_UNIT_COUNTER_WIDTH = 0
       C_TRIG3_UNIT_MATCH_TYPE = "basic"
       C_TRIG4_UNITS = 0
       C_TRIG4_TRIGGER_IN_WIDTH = 8
       C_TRIG4_UNIT_COUNTER_WIDTH = 0
       C_TRIG4_UNIT_MATCH_TYPE = "basic"
       C_TRIG5_UNITS = 0
       C_TRIG5_TRIGGER_IN_WIDTH = 8
       C_TRIG5_UNIT_COUNTER_WIDTH = 0
       C_TRIG5_UNIT_MATCH_TYPE = "basic"
       C_TRIG6_UNITS = 0
       C_TRIG6_TRIGGER_IN_WIDTH = 8
       C_TRIG6_UNIT_COUNTER_WIDTH = 0
       C_TRIG6_UNIT_MATCH_TYPE = "basic"
       C_TRIG7_UNITS = 0
       C_TRIG7_TRIGGER_IN_WIDTH = 8
       C_TRIG7_UNIT_COUNTER_WIDTH = 0
       C_TRIG7_UNIT_MATCH_TYPE = "basic"
       C_TRIG9_TRIGGER_IN_WIDTH = 8
       C_TRIG8_TRIGGER_IN_WIDTH = 8
       C_TRIG8_UNIT_COUNTER_WIDTH = 0
       C_TRIG8_UNIT_MATCH_TYPE = "basic"
       C_TRIG9_UNITS = 0
       C_TRIG8_UNITS = 0
       C_TRIG9_UNIT_COUNTER_WIDTH = 0
       C_TRIG9_UNIT_MATCH_TYPE = "basic"
       C_TRIG10_UNITS = 0
       C_TRIG10_TRIGGER_IN_WIDTH = 8
       C_TRIG10_UNIT_COUNTER_WIDTH = 0
       C_TRIG10_UNIT_MATCH_TYPE = "basic"
       C_TRIG11_UNITS = 0
       C_TRIG11_TRIGGER_IN_WIDTH = 8
       C_TRIG11_UNIT_COUNTER_WIDTH = 0
       C_TRIG11_UNIT_MATCH_TYPE = "basic"
       C_TRIG12_UNITS = 0
       C_TRIG12_TRIGGER_IN_WIDTH = 8
       C_TRIG12_UNIT_COUNTER_WIDTH = 0
       C_TRIG12_UNIT_MATCH_TYPE = "basic"
       C_TRIG13_UNITS = 0
       C_TRIG13_TRIGGER_IN_WIDTH = 8
       C_TRIG13_UNIT_COUNTER_WIDTH = 0
       C_TRIG13_UNIT_MATCH_TYPE = "basic"
       C_TRIG14_UNITS = 0
       C_TRIG14_TRIGGER_IN_WIDTH = 8
       C_TRIG14_UNIT_COUNTER_WIDTH = 0
       C_TRIG14_UNIT_MATCH_TYPE = "basic"
       C_TRIG15_UNITS = 0
       C_TRIG15_TRIGGER_IN_WIDTH = 8
       C_TRIG15_UNIT_COUNTER_WIDTH = 0
       C_TRIG15_UNIT_MATCH_TYPE = "basic"
   WARNING:Xst:2211 -
   "C:/Projects/Crashtest/Leon_withPPC_minimal_gtech_big_gates_1_fault_dynamic-t
   racebuffer-1_run/hdl/cs_edk_port_mapper/cs_edk_port_mapper_chipscope_ila_0.vh
   d" line 257: Instantiating black box module <cs_coregen_chipscope_ila_0>.
       Set user-defined property "C_DATA_IN_WIDTH =  32" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_DATA_SAME_AS_TRIGGER =  1" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>
.
       Set user-defined property "C_DISABLE_RPM =  0" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_ENABLE_TRIGGER_OUT =  1" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_FAMILY =  virtex2p" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_NUM_DATA_SAMPLES =  512" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG0_TRIGGER_IN_WIDTH =  1" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG0_UNIT_COUNTER_WIDTH =  0" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG0_UNIT_MATCH_TYPE =  basic" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG0_UNITS =  1" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG10_TRIGGER_IN_WIDTH =  8" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG10_UNIT_COUNTER_WIDTH =  0" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG10_UNIT_MATCH_TYPE =  basic" for
   instance <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG10_UNITS =  0" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG11_TRIGGER_IN_WIDTH =  8" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG11_UNIT_COUNTER_WIDTH =  0" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG11_UNIT_MATCH_TYPE =  basic" for
   instance <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG11_UNITS =  0" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG12_TRIGGER_IN_WIDTH =  8" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG12_UNIT_COUNTER_WIDTH =  0" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG12_UNIT_MATCH_TYPE =  basic" for
   instance <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG12_UNITS =  0" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG13_TRIGGER_IN_WIDTH =  8" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG13_UNIT_COUNTER_WIDTH =  0" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG13_UNIT_MATCH_TYPE =  basic" for
   instance <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG13_UNITS =  0" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG14_TRIGGER_IN_WIDTH =  8" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG14_UNIT_COUNTER_WIDTH =  0" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG14_UNIT_MATCH_TYPE =  basic" for
   instance <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG14_UNITS =  0" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG15_TRIGGER_IN_WIDTH =  8" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG15_UNIT_COUNTER_WIDTH =  0" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined
property "C_TRIG15_UNIT_MATCH_TYPE =  basic" for
   instance <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG15_UNITS =  0" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG1_TRIGGER_IN_WIDTH =  64" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG1_UNIT_COUNTER_WIDTH =  0" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG1_UNIT_MATCH_TYPE =  basic" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG1_UNITS =  1" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG2_TRIGGER_IN_WIDTH =  1" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG2_UNIT_COUNTER_WIDTH =  0" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG2_UNIT_MATCH_TYPE =  basic" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG2_UNITS =  1" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG3_TRIGGER_IN_WIDTH =  64" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG3_UNIT_COUNTER_WIDTH =  0" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG3_UNIT_MATCH_TYPE =  basic" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG3_UNITS =  1" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG4_TRIGGER_IN_WIDTH =  8" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG4_UNIT_COUNTER_WIDTH =  0" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG4_UNIT_MATCH_TYPE =  basic" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG4_UNITS =  0" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG5_TRIGGER_IN_WIDTH =  8" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG5_UNIT_COUNTER_WIDTH =  0" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG5_UNIT_MATCH_TYPE =  basic" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG5_UNITS =  0" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG6_TRIGGER_IN_WIDTH =  8" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG6_UNIT_COUNTER_WIDTH =  0" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG6_UNIT_MATCH_TYPE =  basic" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG6_UNITS =  0" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG7_TRIGGER_IN_WIDTH =  8" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG7_UNIT_COUNTER_WIDTH =  0" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG7_UNIT_MATCH_TYPE =  basic" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG7_UNITS =  0" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG8_TRIGGER_IN_WID
TH =  8" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG8_UNIT_COUNTER_WIDTH =  0" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG8_UNIT_MATCH_TYPE =  basic" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG8_UNITS =  0" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG9_TRIGGER_IN_WIDTH =  8" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG9_UNIT_COUNTER_WIDTH =  0" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG9_UNIT_MATCH_TYPE =  basic" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
       Set user-defined property "C_TRIG9_UNITS =  0" for instance
   <i_cs_coregen_chipscope_ila_0> in unit <chipscope_ila>.
   Entity <chipscope_ila> analyzed. Unit <chipscope_ila> generated.


   =========================================================================
   *                           HDL Synthesis                               *
   =========================================================================

   Performing bidirectional port resolution...

   Synthesizing Unit <chipscope_ila>.
       Related source file is
   "C:/Projects/Crashtest/Leon_withPPC_minimal_gtech_big_gates_1_fault_dynamic-t
   racebuffer-1_run/hdl/cs_edk_port_mapper/cs_edk_port_mapper_chipscope_ila_0.vh
   d".
   WARNING:Xst:647 - Input <TRIG10> is never used.
   WARNING:Xst:647 - Input <TRIG11> is never used.
   WARNING:Xst:647 - Input <TRIG12> is never used.
   WARNING:Xst:647 - Input <TRIG13> is never used.
   WARNING:Xst:647 - Input <TRIG14> is never used.
   WARNING:Xst:647 - Input <TRIG15> is never used.
   WARNING:Xst:647 - Input <TRIG4> is never used.
   WARNING:Xst:647 - Input <TRIG5> is never used.
   WARNING:Xst:647 - Input <TRIG6> is never used.
   WARNING:Xst:647 - Input <TRIG7> is never used.
   WARNING:Xst:647 - Input <TRIG8> is never used.
   WARNING:Xst:647 - Input <TRIG9> is never used.
   WARNING:Xst:647 - Input <DATA> is never used.
   Unit <chipscope_ila> synthesized.


   =========================================================================
   HDL Synthesis Report

   Found no macro
   =========================================================================

   =========================================================================
   *                       Advanced HDL Synthesis                          *
   =========================================================================

   Executing edif2ngd -noa
   "C:\Projects\Crashtest\Leon_withPPC_minimal_gtech_big_gates_1_fault_dynamic-t
   racebuffer-1_run\implementation\chipscope_ila_0_wrapper\cs_coregen_chipscope_
   ila_0.edn"
   "C:\Projects\Crashtest\Leon_withPPC_minimal_gtech_big_gates_1_fault_dynamic-t
   racebuffer-1_run\implementation\chipscope_ila_0_wrapper\cs_coregen_chipscope_
   ila_0.ngo"
   Release 9.1.02i - edif2ngd J.30
   Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
   INFO:NgdBuild - Release 9.1.02i edif2ngd J.30
   INFO:NgdBuild - Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
   Applying constraints in
   "C:/Projects/Crashtest/Leon_withPPC_minimal_gtech_big_gates_1_fault_dynamic-t
   rac
   ebuffer-1_run/implementation/chipscope_ila_0_wrapper/cs_coregen_chipscope_ila
   _0.
   ncf" to module "cs_coregen_chipscope_ila_0"...
   Writing module to
   "C:/Projects/Crashtest/Leon_withPPC_minimal_gtech_big_gates_1_fault_dynamic-t
   rac
   ebuffer-1_run/implementation/chipscope_ila_0_wrapper/cs_coregen_chipscope_ila
   _0.
   ngo"...
   WARNING:Xst:1474 - Core <cs_coregen_chipscope_ila_0> was not loaded for
   <i_cs_coregen_chipscope_ila_0> as one or more ports did not line up with
   component declaration.  Declared input port <control<35>> was not found in
   the core.  Please make sure that component declaration ports
are consistent
   with the core ports including direction and bus-naming conventions.
   Loading device for application Rf_Device from file '2vp30.nph' in environment
   C:\Xilinx91i.

   =========================================================================
   Advanced HDL Synthesis Report

   Found no macro
   =========================================================================

   =========================================================================
   *                         Low Level Synthesis                           *
   =========================================================================

   Optimizing unit <chipscope_ila> ...

   Mapping all equations...
   Building and optimizing final netlist ...

   Final Macro Processing ...

   =========================================================================
   Final Register Report

   Found no macro
   =========================================================================

   =========================================================================
   *                          Partition Report                             *
   =========================================================================

   Partition Implementation Status
   -------------------------------

     No Partitions were found in this design.

   -------------------------------

   =========================================================================
   *                            Final Report                               *
   =========================================================================
   Final Results
   Top Level Output File Name         :
   ../implementation/chipscope_ila_0_wrapper/chipscope_ila.ngc
   Output Format                      : ngc
   Optimization Goal                  : speed
   Keep Hierarchy                     : no

   Design Statistics
   # IOs                              : 296

   Cell Usage :
   # Others                           : 1
   #      cs_coregen_chipscope_ila_0  : 1
   =========================================================================

   Device utilization summary:
   ---------------------------

   Selected Device : 2vp30ff896-7

    Number of Slices:                       0  out of  13696     0%  
    Number of IOs:                        296
    Number of bonded IOBs:                  0  out of    556     0%  

   ---------------------------
   Partition Resource Summary:
   ---------------------------

     No Partitions were found in this design.

   ---------------------------


   =========================================================================
   TIMING REPORT

   NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
         FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
         GENERATED AFTER PLACE-and-ROUTE.

   Clock Information:
   ------------------
   No clock signals found in this design

   Asynchronous Control Signals Information:
   ----------------------------------------
   No asynchronous control signals found in this design

   Timing Summary:
   ---------------
   Speed Grade: -7

      Minimum period: No path found
      Minimum input arrival time before clock: No path found
      Maximum output required time after clock: No path found
      Maximum combinational path delay: 0.000ns

   Timing Detail:
   --------------
   All values displayed in nanoseconds (ns)

   =========================================================================
   Timing constraint: Default path analysis
     Total number of paths / destination ports: 168 / 168
   -------------------------------------------------------------------------
   Delay:               0.000ns (Levels of Logic = 0)
     Source:            i_cs_coregen_chipscope_ila_0:trig_out (PAD)
     Destination:       TRIG_OUT (PAD)

     Data Path: i_cs_coregen_chipscope_ila_0:trig_out to TRIG_OUT
                                   Gate     Net
       Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
       ----------------------------------------  ------------
       cs_coregen_chipscope_ila_0:
trig_out    0   0.000   0.000
   i_cs_coregen_chipscope_ila_0 (TRIG_OUT)
       ----------------------------------------
       Total                      0.000ns (0.000ns logic, 0.000ns route)

   =========================================================================
   WARNING:Xst:616 - Invalid property "C_DATA_IN_WIDTH 32": Did not attach to
   i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_DATA_SAME_AS_TRIGGER 1": Did not attach
   to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_DISABLE_RPM 0": Did not attach to
   i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_ENABLE_TRIGGER_OUT 1": Did not attach
   to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_FAMILY virtex2p": Did not attach to
   i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_NUM_DATA_SAMPLES 512": Did not attach
   to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG0_TRIGGER_IN_WIDTH 1": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG0_UNIT_COUNTER_WIDTH 0": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG0_UNIT_MATCH_TYPE basic": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG0_UNITS 1": Did not attach to
   i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG10_TRIGGER_IN_WIDTH 8": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG10_UNIT_COUNTER_WIDTH 0": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG10_UNIT_MATCH_TYPE basic": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG10_UNITS 0": Did not attach to
   i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG11_TRIGGER_IN_WIDTH 8": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG11_UNIT_COUNTER_WIDTH 0": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG11_UNIT_MATCH_TYPE basic": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG11_UNITS 0": Did not attach to
   i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG12_TRIGGER_IN_WIDTH 8": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG12_UNIT_COUNTER_WIDTH 0": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG12_UNIT_MATCH_TYPE basic": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG12_UNITS 0": Did not attach to
   i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG13_TRIGGER_IN_WIDTH 8": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG13_UNIT_COUNTER_WIDTH 0": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG13_UNIT_MATCH_TYPE basic": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG13_UNITS 0": Did not attach to
   i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG14_TRIGGER_IN_WIDTH 8": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG14_UNIT_COUNTER_WIDTH 0": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG14_UNIT_MATCH_TYPE basic": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG14_UNITS 0": Did not attach to
   i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG15_TRIGGER_IN_WIDTH 8": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG15_UNIT_COUNTER_WIDTH 0": Did not
   attach to i_cs_coregen_chipscope_ila_
0.
   WARNING:Xst:616 - Invalid property "C_TRIG15_UNIT_MATCH_TYPE basic": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG15_UNITS 0": Did not attach to
   i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG1_TRIGGER_IN_WIDTH 64": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG1_UNIT_COUNTER_WIDTH 0": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG1_UNIT_MATCH_TYPE basic": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG1_UNITS 1": Did not attach to
   i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG2_TRIGGER_IN_WIDTH 1": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG2_UNIT_COUNTER_WIDTH 0": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG2_UNIT_MATCH_TYPE basic": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG2_UNITS 1": Did not attach to
   i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG3_TRIGGER_IN_WIDTH 64": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG3_UNIT_COUNTER_WIDTH 0": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG3_UNIT_MATCH_TYPE basic": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG3_UNITS 1": Did not attach to
   i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG4_TRIGGER_IN_WIDTH 8": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG4_UNIT_COUNTER_WIDTH 0": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG4_UNIT_MATCH_TYPE basic": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG4_UNITS 0": Did not attach to
   i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG5_TRIGGER_IN_WIDTH 8": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG5_UNIT_COUNTER_WIDTH 0": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG5_UNIT_MATCH_TYPE basic": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG5_UNITS 0": Did not attach to
   i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG6_TRIGGER_IN_WIDTH 8": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG6_UNIT_COUNTER_WIDTH 0": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG6_UNIT_MATCH_TYPE basic": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG6_UNITS 0": Did not attach to
   i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG7_TRIGGER_IN_WIDTH 8": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG7_UNIT_COUNTER_WIDTH 0": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG7_UNIT_MATCH_TYPE basic": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG7_UNITS 0": Did not attach to
   i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG8_TRIGGER_IN_WIDTH 8": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG8_UNIT_COUNTER_WIDTH 0": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG8_UNIT_MATCH_TYPE basic": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG8_UNITS 0": Did not attach to
   i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG9_TRIGGER_IN_WIDTH 8": Did not
   attach to i_cs_core
gen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG9_UNIT_COUNTER_WIDTH 0": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG9_UNIT_MATCH_TYPE basic": Did not
   attach to i_cs_coregen_chipscope_ila_0.
   WARNING:Xst:616 - Invalid property "C_TRIG9_UNITS 0": Did not attach to
   i_cs_coregen_chipscope_ila_0.
   CPU : 8.52 / 8.66 s | Elapsed : 9.00 / 9.00 s

   -->

   Total memory usage is 190132 kilobytes

   Number of errors   :    0 (   0 filtered)
   Number of warnings :   88 (   0 filtered)
   Number of infos    :    0 (   0 filtered)

   WARNING:UtilitiesC:159 - Message file "HDLSynthesis.msg" wasn't found.
   WARNING:HDLSynthesis - You are using an evaluation version of Xilinx
   Software.
      In 351 days, this program will not operate. For more information about
   this
      product, please refer to the Evaluation Agreement, which was shipped to
   you
      along with the Evaluation CDs.
      To purchase an annual license for this software, please contact your local
      Field Applications Engineer (FAE) or salesperson. If you have any
   questions,
      or if we can assist in any way, please send an email to: eval@xilinx.com
      Thank You!
       while executing
   "exec xst -ifn $xst_scr_filename"
       (procedure "synthesize_cs_edk_port_mapper_core" line 56)
       invoked from within
   "synthesize_cs_edk_port_mapper_core $param_table"
       (procedure "::hw_chipscope_ila_v1_01_a::ila_generate" line 131)
       invoked from within
   "::hw_chipscope_ila_v1_01_a::ila_generate 41234072"
**********************************************
**********************************************
Created elaborate directory
INFO: Chipscope core parameters not changed. Not regenerating core
ERROR:MDT - platgen failed with errors!

make: *** [implementation/system.bmm] Error 2

Done!
0 Kudos
2 Replies
Visitor eliezerm
Visitor
7,908 Views
Registered: ‎04-15-2008

Re: Chipscope XPS 9.1 issues

hello,

 

did you connect the triger port to a data source?

did you connect the clock to the core?

 

can you send MHS file? 

 

Eliezer 

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Visitor azarias
Visitor
7,895 Views
Registered: ‎09-28-2007

Re: Chipscope XPS 9.1 issues

Thanks for the reply!

I fixed the problem, it was related to the fact that I'm using an evaluation version of the Xilinx Tools:

 

http://www.groupsrv.com/computers/about384159.html 

 

From the link:

....
In the file chipscope_plb_iba_v1_01_a/data/chipscope_plb_iba_v2_1_0.tcl
I had to change:
exec xst -ifn $xst_scr_filename
to:
exec xst -ifn $xst_scr_filename 2> null
so the warning about the evaluation version expiring doesn't cause the
compile to fail. 

... 

 

~Andrea 

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