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Registered: ‎05-30-2008

Clock Generator GUI configuration has bug when selecting certain memory parts in EDK 11.3 and 11.4

I was unable to find any information on this when I had the problem so I created a webcase. It has now been "solved" so I am posting this information in order to help others and also offload the work of Xilinx FAEs having to deal with unecessary webcases regarding this EDK bug.


Details of my webcase:



MPMC and clock generator are configured for the SP601 memory part, EDE1116ACBG-8E. I change the memory part to MT46H64M16XXXX-5L-IT and clock generator gives the error listed below. After clicking YES, the error appears again. After clicking many times, the clock generator configuration comes up. The MPMC clock settings are grayed out and do not allow entries. The clock generator does not allow changing tabs and says that MPMC clock settings must be entered. Looking at MPMC config, the period is set to 11,111 ps, corresponding to 90 MHz sys_clk_s just as it was for the other memory part. After this error I manually set the memory clocks 2x and 2x_180 to 180 MHz to double the 90 MHz bus speed without any change in the error. I tried this whole procedure last week with version 11.3 and after changing the memory part, the clock generator configuration would not come up at all due to an error (the second error listed below). After updating to 11.4, I get the behavior experience above. If I change the part back to EDE1116ACBG-8E, everything works fine again. I am confused as to why the error says "The MPMC clock speed must be from <-0.000001> to <-0.000001> MHz." This is clearly inaccurate. I have tried several other memory parts and I get the first error for some and the second error for others.
This is from the Error Message (1)
The bus clock <90.000000> for the MPMC is invalid. The MPMC runs at a ratio of 1:1 or 2:1 of the bus. The MPMC clock speed must be from <-0.000001> to <-0.000001> MHz.

Do you still want to continue?

This is from the Error Message (2)

A Xilinx Application has encountered an unexpected error. It is recommended that you save any unsaved work in the event that this condition persists. for further assistance, please consult the Answers Database and other online resources at http://support.xilinx.com.
This is from the Steps to Reproduce Problem
Change the memory part in MPMC from EDE1116ACBG-8E to MT46H64M16XXXX-5L-IT and try to use clock generator.





Some memory parts work fine but many do not. I tried a variety. Every EDE one I tried worked. Some MT parts worked and others did not. No LPDDR parts worked. The part I am trying to use is a LPDDR part.





 Xilinx response:


The clock generator bug you are running into just started to come up in the 11.4 tools. Currently the workaround is to manually modify the MHS rather than using the GUI. The tools should still generate valid hardware, but you will not be able to configure the clock generator from the GUI.




My response:


Well I also experienced it in 11.3 and updated in hopes of fixing it,
but it instead gave me a more meaningful error instead of just a generic
one. OK, I guess I will just use the MHS. I have already done this in
hopes it would fix the GUI bug, but it did not. Unfortunately there is
no way to "verify clocks", but I guess if it builds then the settings

Is there any way to be notified when this bug is fixed or do I just need
to try again after the next update?




Xilinx Repsonse:


 We do not have an automatic way to notify you when the fix is complete, but you can track it with the change request number. The number is 541698. If you create a case in the future asking for the status of CR 541698 we can let you know the progress. I expect that this will be marked a high priority and will likely be chosen to be fixed in the 12.1 release since this week alone we have received three cases already on the problem.





I hope this is helpful to someone.








Message Edited by thirdeye on 12-15-2009 10:45 AM