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zuwashi
Visitor
Visitor
2,777 Views
Registered: ‎10-21-2011

Clock generator and clock synthesys

Hi Everyone,

I have a small problem with my design. I have an External clock source at 105 mhz. I need 3 clocks in my system: 26.25mhz, 26.25 mhz (whit a 90 degree phase shift) and 6.5625mhz.

when i try to synthesize the system, i get an error. This is the content of clock_generator_o.log:

 

Clock generation result : FAILED

 

------------------------------------------------------------------------------
C_FAMILY = virtex4

C_CLKIN_FREQ = 105000000

C_CLKFBIN_FREQ = 0

C_CLKFBOUT_FREQ = 0
C_CLKFBOUT_BUF = TRUE

C_CLKOUT0_FREQ = 26250000
C_CLKOUT0_PHASE = 0
C_CLKOUT0_GROUP = NONE
C_CLKOUT0_BUF = TRUE

C_CLKOUT1_FREQ = 26250000
C_CLKOUT1_PHASE = 90
C_CLKOUT1_GROUP = NONE
C_CLKOUT1_BUF = TRUE

C_CLKOUT2_FREQ = 6562500
C_CLKOUT2_PHASE = 0
C_CLKOUT2_GROUP = NONE
C_CLKOUT2_BUF = TRUE

 


------------------------------------------------------------------------------
ERROR:

CLKOUT1 can not be generated alone from the clock input

 

I can't explain why, since I have no problem when i set the clock values to 100,100 (with 90 phase shift) and 25 Mhz.


I have also tried to generate some of the clock using an additional DCM (several different configuration), but i get timing constraints error.

Thanks for your answers. 

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2 Replies
golson
Scholar
Scholar
2,776 Views
Registered: ‎04-07-2008

I think the problem is likely that you are creating too slow a frequency for the Clock Generator.  You could use logic to create your slow clocks from a higher frequency clock.  You did say you were able to create a 25 mhz clock though.  What chip family are you targeting.  I think that 6 Mhz would probably be too slow.

 

Also there is a related posting: Which says the M/D ratio may not be able to match the frequency you are trying to achieve.

 

http://forums.xilinx.com/t5/Embedded-Processing/convert-ucf-pl-missing-Spartan6-option/m-p/122624#M3941

 

 

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zuwashi
Visitor
Visitor
2,751 Views
Registered: ‎10-21-2011

Thanks for your answer.


I don't think the problem is in the frequency.
The report i posted in the previous post tells that the clock that is causing the problem is C_CLKOUT1, not C_CLKOUT2 (and btw you can synthetize it by setting N = 2 and D = 32).

The problem is in the phase shift, but i can't understand why.

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