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rebelsequeira
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Registered: ‎09-30-2019

Code hangs at Xil_Out32

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I am trying to do a simple LED blink via GPIO. I have attached images of my block design, Address editor for the axi_gpio and the constraints file. I am using XSDK 2019.1 and Vivado 2019.1. I am trying to run this on an UltraZed board by Avnet. The code is as below. While trying to set the direction of the GPIO I keep running into the issue where it tries to do this  --> *LocalAddr = Value; in Xil_Out32 and it hangs. Based on the comments from this post --> https://forums.xilinx.com/t5/Vivado-TCL-Community/Stuck-at-Xil-Out32/m-p/471656#M1612 I modified the constraints for each led output but I still run into the issue. I also tried changing the optimization to O0 in the bsp as LocalAddr appears as N/A while watching it. Is there anyway to resolve this?

#include <stdio.h>
#include "platform.h"
#include "xparameters.h"
#include "xgpio.h"
#include "xstatus.h"

#define GPIO_DEVICE_ID XPAR_AXI_GPIO_0_DEVICE_ID
#define LED 0x01
#define LED_DELAY 100000000
#define LED_CHANNEL 1

XGpio Gpio; // Instantiated GPIO device driver instance

int LEDOutput()

{
volatile int Delay;
int Status;
int led = LED;
Status = XGpio_Initialize(&Gpio, GPIO_DEVICE_ID);
if ( Status != XST_SUCCESS ) { return XST_FAILURE; }

//Set direction for the LED output
XGpio_SetDataDirection(&Gpio, LED_CHANNEL, 0x00);

//Infinitive loop to blink LEDs
while (1) {
while(led<=128){
// write output to the LEDs
XGpio_DiscreteWrite(&Gpio, LED_CHANNEL, led);
// Delay so that LEDs blinking is visible
led = led<<1;
for (Delay = 0; Delay < LED_DELAY; Delay++) {;}
}
led=LED;

}
printf("Oop! Never get into here\n\r");
return XST_SUCCESS;

}

 

int main()

{

int Status;
init_platform();
Status = LEDOutput();
if ( Status != XST_SUCCESS) {
print("GPIO output the the LEDs failed!\n\r");

}
cleanup_platform();
return 0;

}

2019-10-16 22_32_10-GPIO_Test2 - [C__Users_rebel.sequeira_Documents_dev_Ultrascale-Freertos_Vivado_G.png
2019-10-16 22_33_14-GPIO_Test2 - [C__Users_rebel.sequeira_Documents_dev_Ultrascale-Freertos_Vivado_G.png
2019-10-16 22_33_31-GPIO_Test2 - [C__Users_rebel.sequeira_Documents_dev_Ultrascale-Freertos_Vivado_G.png
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ibaie
Xilinx Employee
Xilinx Employee
685 Views
Registered: ‎10-06-2016

Hi @rebelsequeira 

How are you running your application code in the target? using the debugger or creating a boot image? It seems for me that you might have the bitstream non prorgrammed, so any attempt to access tot the memory address of AXI GPIO IP will hang the interconnect.

Regards


Ibai
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3 Replies
ibaie
Xilinx Employee
Xilinx Employee
686 Views
Registered: ‎10-06-2016

Hi @rebelsequeira 

How are you running your application code in the target? using the debugger or creating a boot image? It seems for me that you might have the bitstream non prorgrammed, so any attempt to access tot the memory address of AXI GPIO IP will hang the interconnect.

Regards


Ibai
Don’t forget to reply, kudo, and accept as solution.

View solution in original post

stephenm
Moderator
Moderator
671 Views
Registered: ‎09-12-2007

If booting then make sure the bitstream is added to the bif file. If from SDK, then in the debug configurations, make sure that the program fpga box is ticked. As Ibai said this is most likely due to the debuggerr trying to access a register that doesnt exist.

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rebelsequeira
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Registered: ‎09-30-2019

I got it to work . One of the issues seemed that I wasn't programming the FPGA. Thanks for the help

The other issue is my constraints are not getting set. I used this command "write_xdc -no_fixed_only -constraints all <file_name_and_path>" to read my constraints and I have default constraints. I had to manually change each pin constraints in the schematic pin I/O properties. Is this how it needs to be done or should it by default pick the constraints from my target constraints file?

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