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Contributor
Contributor
8,509 Views
Registered: ‎09-05-2014

Combining SDK C file and verilog to make a prom file

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Hello,

 

How do I combine my C file that I created in SDK with the Verilog files that I created in ISE as a .bit file or a .mcs file ? That is, when I burn the project into my fpga, let's say I have an LED blink routine that I wrote in C for a uBlaze instantiated in ISE, the leds must start blinking immediately rather than waiting for me to execute the C code (like I'm doing now) ?

 

Thank you

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Scholar sampatd
Scholar
15,640 Views
Registered: ‎09-05-2011

Re: Combining SDK C file and verilog to make a prom file

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Use data2mem command to combine the .bit file from ISE and the .elf application file to create a new .bit file

system.bit + application.elf -----> download.bit

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/data2mem.pdf

Next, use this (download.bit) .bit file with impact to create an mcs file.
https://www.digilentinc.com/Data/Documents/Tutorials/MCS%20File%20Creation%20with%20Xilinx%20ISE%20Tutorial.pdf

4 Replies
Scholar sampatd
Scholar
15,641 Views
Registered: ‎09-05-2011

Re: Combining SDK C file and verilog to make a prom file

Jump to solution

Use data2mem command to combine the .bit file from ISE and the .elf application file to create a new .bit file

system.bit + application.elf -----> download.bit

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/data2mem.pdf

Next, use this (download.bit) .bit file with impact to create an mcs file.
https://www.digilentinc.com/Data/Documents/Tutorials/MCS%20File%20Creation%20with%20Xilinx%20ISE%20Tutorial.pdf

Contributor
Contributor
8,466 Views
Registered: ‎09-05-2014

Re: Combining SDK C file and verilog to make a prom file

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Thank you, will try this and get back ! :D

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Xilinx Employee
Xilinx Employee
8,458 Views
Registered: ‎08-02-2007

Re: Combining SDK C file and verilog to make a prom file

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hi,

 

you can refer to this procedure to integrate ISE design with a Embedded Sub-system.

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/edk_ctt.pdf

 

If your C application is running from BRAM's inside the design, you need to run promgen to generate a MCS file that will use the updated bitstream with your software application. Once you program the PROM with MCS both the hardware design along with the processor C application will start executing

 

--hem

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Contributor
Contributor
8,280 Views
Registered: ‎09-05-2014

Re: Combining SDK C file and verilog to make a prom file

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Hi,

 

An easier technique that also works is the following:

If the processor is a submodule in ISE, one can add the elf file to the heirarchy. Once the file is added , a pop-up appears where one has to select an option which will link the elf file to the implementation (i dont remember the exact verbose ;)). Then, generate prog file will generate a bit file with the software+processor+logic info in it. This can be used to generate the mcs file.

 

Thank you !

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