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jimg@crypto4a.com
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Registered: ‎05-11-2018

Configuring CSU clock rate via CSU_PLL_CTRL register

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Hello,

I'm trying to do some performance characterization of the ZYNQ Ultrascale MPSoC's CSU RSA HW accelerator in a bare metal configuration.  Using the Xilsecure driver, it's pretty easy to setup a timing loop to measure the raw performance of the HW for various operand sizes which is great. However, I'd like to modify the clock rate of the CSU to see just how far I can push performance, but I seem to be missing something in my setup that I'm hoping someone with some experience/knowledge can correct.

I'm assuming the clock rate of the CSU is being governed post secure boot via the CSU_PLL_REGISTER in the CRL_APB register block. In the online ZYNQ MPSoC register reference there is only the bare minimum of information provided:

  • Bits [2:0] = SRCSEL which appear to choose your clock generator input source (0 = IOPLL, 2 = RPLL, 3 = DPLL_CLK_TO_LPD)
  • Bits [13:8] = 6-bit divider (I'm guessing this divides down the clock generator input source but hey, why take all the mystery out of it and actually explain how this works in the reference... gotta keep it interesting I guess!)
  • Bit [24] = clock active control (0 = disable, 1 = enable) (oh joy, more unexplained parameters... I'm not sure what this does but it's set to 1 by default so probably best we leave it that way)

That's it.  No real explanation is given as to how to go about safely changing the CSU clock frequency, or what, if any, constraints there may be on the process. Looking at PG201 it appears the CSU can have a clock frequency in the range [0, 400] MHz based on the valid range of PSU_CRL_APG_CSU_PLL_CTRL_FREQMHZ in Table C-1. I naively assumed it was as simple as programming a new divider value based on the simple equation F_csu = F_src / divider (e.g., in my design IOPLL is 3GHz with a divide-by-two output so F_src=1500 MHz, so a divider value of 4 would give me a 375MHz CSU clock). However, after boot my CSU_PLL_CTRL register is set to 0x01000800 (src=IOPLL, divider = 8 so F_csu = 187.5MHz), and if I change its value to 0x01000400 I measure the exact same performance as I had with the original settings despite thinking I had doubled the CSU's operating frequency.

Obviously I'm doing something wrong here as in wp512 WolfSSL reported they could get the CSU operating at 375MHz, so apparently it can be done. Furthermore, when I compare my performance measurements to theirs for RSA2048/RSA4096 decryption operations there is a discrepancy that seems to indicate there is indeed ~2x reduction in performance, which is as expected given the reset settings of the CSU_PLL_CTRL register.

  • RSA2048 private key operation: 12.85 ms (WolfSSL) vs 25.97 ms (mine)
  • RSA4096 private key operation: 95.9 ms (WolfSSL) vs 201.41 ms (mine)

So what's the magic?! What obvious thing am I missing here? Please let me know. Thanks!

FYI - I'm doing all of my experiments on a XCZU9EG using SDK 2018.2 and a bare metal environment (and Linux or an RTOS are not options for me sadly).

Take care and thanks in advance to any assistance anyone is able to provide

  Jim

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jimg@crypto4a.com
Adventurer
Adventurer
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Registered: ‎05-11-2018

Hello me, it's me again (my apologies to Dave Mustaine for plagiarizing his lyric),

With some timely assistance from the developers at WolfSSL who authored wp512, I was able to solve my own problem.

It turns out I was missing a key step in configuring the CSU: bit 0 of the CSU control register (0xFFCA0004) needs to be set to 1 to select the CSU PLL as the CSU clock source. I wasn't aware of this setting so the CSU was always being clocked from the internal system oscillator, hence my efforts to manipulate the CSU PLL output frequency were irrelevant as that wasn't what was clocking the CSU logic. By setting the aforementioned clock source control bit I now see the performance of the CSU matching what has been configured in the CSU PLL control register.

So to summarize, you can control the CSU clock rate by doing the following:

  • Set bit 0 of the CSU control register (0xFFCA0004) to 1 to select the CSU clock to be the CSU PLL output.
  • Configure the CSU PLL control register (0xFF5E00A0) to configure the CSU PLL to the desired clock frequency.

Take care, and thanks again to Jacob and Todd at WolfSSL for their assistance with this!

  Jim

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jimg@crypto4a.com
Adventurer
Adventurer
264 Views
Registered: ‎05-11-2018

Hello me, it's me again (my apologies to Dave Mustaine for plagiarizing his lyric),

With some timely assistance from the developers at WolfSSL who authored wp512, I was able to solve my own problem.

It turns out I was missing a key step in configuring the CSU: bit 0 of the CSU control register (0xFFCA0004) needs to be set to 1 to select the CSU PLL as the CSU clock source. I wasn't aware of this setting so the CSU was always being clocked from the internal system oscillator, hence my efforts to manipulate the CSU PLL output frequency were irrelevant as that wasn't what was clocking the CSU logic. By setting the aforementioned clock source control bit I now see the performance of the CSU matching what has been configured in the CSU PLL control register.

So to summarize, you can control the CSU clock rate by doing the following:

  • Set bit 0 of the CSU control register (0xFFCA0004) to 1 to select the CSU clock to be the CSU PLL output.
  • Configure the CSU PLL control register (0xFF5E00A0) to configure the CSU PLL to the desired clock frequency.

Take care, and thanks again to Jacob and Todd at WolfSSL for their assistance with this!

  Jim

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