UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor ioputaitano
Visitor
1,209 Views
Registered: ‎12-22-2011

Connections VEC[x:0] not visible

Hello Everybody,

 

I am working on an system with several IP cores in XPS 13.4. If I connect them together, everything works fine. But in the graphic, generated by the tool, only the single connection (like std_logic) are shown, and all mulltiple connection (std_logic_vector) get a different color when connected but are not visible.

I made a screenshot in order to explain it better. The ChannelX are connected together. Is it possible to make this lines visible? The unconnected ports are in red. That is ok.

 

Thanks in advance,

 

Greetings Pablo

Screenshot.png
0 Kudos