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moraali
Explorer
Explorer
6,908 Views
Registered: ‎12-06-2007

Convert VHDL codes to a EDK IP ?

Good morning, I have 4 VHDL codes. I want to convert them(4 VHDL codes) into an IP in the EDK 9.2. How can I do it ? Can you explain to me the steps in a simple way? Do you have any reference to guide me? Please explain in a simple was as i am very nes to FPGA world. Thank you
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7 Replies
rickysu
Explorer
Explorer
6,882 Views
Registered: ‎08-12-2007

I guess I can't answer this question very well because it's not a one step job. Not easy for someone new.

 

First, you need to know about your VHDL codes. At least know its function and the top level port functions.

Second, you need to choose the bus for your IP - PLB46 or FSL? - Whether or not you need some advanced function of the bus, such as burst, etc.

Third, if your existing code can work well with the  BUS template generated by the CIP wizard, you just need to connect their ports. But if not, you have to modify the code yourself.

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barriet
Xilinx Employee
Xilinx Employee
6,877 Views
Registered: ‎08-13-2007

XAPP967 can be a useful reference:

http://www.xilinx.com/support/documentation/application_notes/xapp967.pdf (Creating an OPB IPIF-based IP and Using it in EDK)
It was written for EDK 9.1i so it isn't the most current with the EDK 9.2i changes for the new PLB v4.6 infrastructure. But the concepts are similar.

 

You should also review the "Creating Your Own Intellectual Property (IP)"section of the "EDK Concepts, Tools, and Techniques" document. Available in your installation: %XILINX_EDK%\doc\usenglish\edk_ctt.pdf

 

Also available online for 10.1:

http://www.xilinx.com/support/documentation/sw_manuals/edk_ctt.pdf

 

bt

 

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moraali
Explorer
Explorer
6,873 Views
Registered: ‎12-06-2007

Good morning sir,

In the attachment, I have explained of the project system that I want to do. I had read

http://www.xilinx.com/support/documentation/application_notes/xapp967.pdf

http://www.xilinx.com/support/documentation/sw_manuals/edk_ctt.pdf

I have done VHDL codes is ISE 9.2 and it runs very well. Now I want to convert the codes into an IP.

1) Should I create the Core Template? Can I ignore it , and straight away import the VHDL codes into the EDK?

2) If I need to use Core Template, where can I insert my VHDL codes? Should I modify my VHDL codes by inserting them in the generated HDL folder codes? In HDL folder there are user_logic.vhd and LED.vhd. Which one should insert my codes?

Please explain in a simple way as I am new to FPGA world.

Thank you

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moraali
Explorer
Explorer
6,872 Views
Registered: ‎12-06-2007

Good morning sir,

In the attachment, I have explained of the project system that I want to do. I had read

http://www.xilinx.com/support/documentation/application_notes/xapp967.pdf

http://www.xilinx.com/support/documentation/sw_manuals/edk_ctt.pdf

I have done VHDL codes is ISE 9.2 and it runs very well. Now I want to convert the codes into an IP.

1) Should I create the Core Template? Can I ignore it , and straight away import the VHDL codes into the EDK?

2) If I need to use Core Template, where can I insert my VHDL codes? Should I modify my VHDL codes by inserting them in the generated HDL folder codes? In HDL folder there are user_logic.vhd and LED.vhd. Which one should insert my codes?

Please explain in a simple way as I am new to FPGA world.

Thank you

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pumaju1808
Scholar
Scholar
6,847 Views
Registered: ‎08-14-2007

hi,

 

in the guides that you read, you can realized that you should manipulate user_logic.vhd file to incorporate your funcionallity, now i think the solution for your problem is to instance your top VHDL as component inside user_logic.vhd, read help of EDK to know how you can import your VHDL files when you are using "Create Import Peripheral" wizard

 

good luck

 

P.D. i recommend that dont expect receive a step by step tutorial, it is hard that someone give to you something like that

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moraali
Explorer
Explorer
6,656 Views
Registered: ‎12-06-2007

I unable to receive hyperterminal input. Based on the coding below I can send , but can not receive the information . How can I rectify this problem?

 

  

#include "xparameters.h"
#include "xuartlite.h"

#define UART_BASEADDR XPAR_UARTLITE_0_BASEADDR
#define ESCAPE 0x1b


static void myprintf (char *s)
{
  while (*s)
  {
 XUartLite_SendByte (UART_BASEADDR ,*s );
        s++;
  }
}

void echo()
{
 char s;
 
 do
 {
   s = XUartLite_RecvByte(UART_BASEADDR); // Does s receive the string?
  
  
   if (s == '\r')
   {
    XUartLite_SendByte (UART_BASEADDR , '\n' ); //It should send back to Hyperterminal, but no output
   }
   
   XUartLite_SendByte (UART_BASEADDR , s ); //It should send back to Hyperterminal, but no output
 } while (s != ESCAPE);
}
int main()
{
 myprintf("Good morning \r\n"); //OK, hyperterminal will display "Good morning"
 echo();                        //NOT OK, hyperterminal will not display "Good morning"
 
 return 0;
}

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moraali
Explorer
Explorer
6,654 Views
Registered: ‎12-06-2007

I unable to receive hyperterminal input. Based on the coding below I can send , but can not receive the information . How can I rectify this problem?

 

  

#include "xparameters.h"
#include "xuartlite.h"

#define UART_BASEADDR XPAR_UARTLITE_0_BASEADDR
#define ESCAPE 0x1b


static void myprintf (char *s)
{
  while (*s)
  {
 XUartLite_SendByte (UART_BASEADDR ,*s );
        s++;
  }
}

void echo()
{
 char s;
 
 do
 {
   s = XUartLite_RecvByte(UART_BASEADDR); // Does s receive the string?
  
  
   if (s == '\r')
   {
    XUartLite_SendByte (UART_BASEADDR , '\n' ); //It should send back to Hyperterminal, but no output
   }
   
   XUartLite_SendByte (UART_BASEADDR , s ); //It should send back to Hyperterminal, but no output
 } while (s != ESCAPE);
}
int main()
{
 myprintf("Good morning \r\n"); //OK, hyperterminal will display "Good morning"
 echo();                        //NOT OK, hyperterminal will not display "Good morning"
 
 return 0;
}

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