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Visitor mbspartan
Visitor
9,773 Views
Registered: ‎07-07-2009

Create or Import IP Peripheral ---- HDL parser error detected

Hello all,

 

Using EDK 9.1 when i try to "create or import peripheral ip" and click finish, i get this error " HDL parser error detected " i tried to search the forum and found a solution as follows;

 

Solution

 

The generated HDL in the "user_logic.vhd" file is incorrect. In order to work around the error, you can edit the .vhd file and import the created files using the CIP Wizard to generate the rest of the files.

Follow these steps to finish the custom IP generation process.
1. Close the CIP wizard by selecting "ok" on the "HDL Parser Error Detected" message box
2. Select the "Cancel" button in the CIP Wizard
3. Open the user_logic.vhd file in the %custom_ip_name%/hdl/vhdl directory
4. Change the following text in the user_logic.vhd file:

from:
IP2Bus_WrAck <= IP2Bus_RdAck <= IP2Bus_Error <= '0';

to:
IP2Bus_Error <= '0';
IP2Bus_RdAck <= '0';
IP2Bus_WrAck <= '0';

5. Use the CIP Wizard to import an existing peripheral using the already-generated .vhd files and the .pao file



But when i located this user_logic.vhdl file the arc looks like this;

 

begin

  --USER logic implementation added here

  ------------------------------------------
  -- Example code to drive IP to Bus signals
  ------------------------------------------
  IP2Bus_Data        <= (others => '0');

  IP2Bus_Ack         <= Bus2IP_WrCE(0) or Bus2IP_RdCE(0);
  IP2Bus_Error       <= '0';
  IP2Bus_Retry       <= '0';
  IP2Bus_ToutSup     <= '0';

end IMP;

 so the lines described dont exist there.....has anyone had experience/solved this problem ?

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8 Replies
Scholar pumaju1808
Scholar
9,770 Views
Registered: ‎08-14-2007

Re: Create or Import IP Peripheral ---- HDL parser error detected

hi,

 

what about the other two signals ("IP2Bus_RdAck" and "IP2Bus_WrAck") what values these signals have?? how is the assignation for these signals

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Visitor mbspartan
Visitor
9,766 Views
Registered: ‎07-07-2009

Re: Create or Import IP Peripheral ---- HDL parser error detected

Hi, Im using a tutorial for the spartan 3E "EDK 9.1 MicroBlaze Tutorial in Virtex-4" and im following the instructions exactly although changing the settings for my spartan 3E.

So this file has been uploaded i didnt assign anything myself....

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Participant nc6
Participant
9,760 Views
Registered: ‎05-07-2009

Re: Create or Import IP Peripheral ---- HDL parser error detected

copy paste the user_logic.vhd file contents. lets see if i can find any errors or workarounds.

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Visitor mbspartan
Visitor
9,757 Views
Registered: ‎07-07-2009

Re: Create or Import IP Peripheral ---- HDL parser error detected

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------

--USER libraries added here

------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
--   C_DWIDTH                     -- User logic data bus width
--   C_NUM_CE                     -- User logic chip enable bus width
--
-- Definition of Ports:
--   Bus2IP_Clk                   -- Bus to IP clock
--   Bus2IP_Reset                 -- Bus to IP reset
--   Bus2IP_Data                  -- Bus to IP data bus for user logic
--   Bus2IP_BE                    -- Bus to IP byte enables for user logic
--   Bus2IP_RdCE                  -- Bus to IP read chip enable for user logic
--   Bus2IP_WrCE                  -- Bus to IP write chip enable for user logic
--   IP2Bus_Data                  -- IP to Bus data bus for user logic
--   IP2Bus_Ack                   -- IP to Bus acknowledgement
--   IP2Bus_Retry                 -- IP to Bus retry response
--   IP2Bus_Error                 -- IP to Bus error response
--   IP2Bus_ToutSup               -- IP to Bus timeout suppress
------------------------------------------------------------------------------

entity user_logic is
  generic
  (
    -- ADD USER GENERICS BELOW THIS LINE ---------------
    --USER generics added here
    -- ADD USER GENERICS ABOVE THIS LINE ---------------

    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- Bus protocol parameters, do not add to or delete
    C_DWIDTH                       : integer              := 32;
    C_NUM_CE                       : integer              := 4
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
  );
  port
  (
    -- ADD USER PORTS BELOW THIS LINE ------------------
    --USER ports added here
    -- ADD USER PORTS ABOVE THIS LINE ------------------

    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- Bus protocol ports, do not add to or delete
    Bus2IP_Clk                     : in  std_logic;
    Bus2IP_Reset                   : in  std_logic;
    Bus2IP_Data                    : in  std_logic_vector(0 to C_DWIDTH-1);
    Bus2IP_BE                      : in  std_logic_vector(0 to C_DWIDTH/8-1);
    Bus2IP_RdCE                    : in  std_logic_vector(0 to C_NUM_CE-1);
    Bus2IP_WrCE                    : in  std_logic_vector(0 to C_NUM_CE-1);
    IP2Bus_Data                    : out std_logic_vector(0 to C_DWIDTH-1);
    IP2Bus_Ack                     : out std_logic;
    IP2Bus_Retry                   : out std_logic;
    IP2Bus_Error                   : out std_logic;
    IP2Bus_ToutSup                 : out std_logic
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
  );
end entity user_logic;

------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------

architecture IMP of user_logic is

  --USER signal declarations added here, as needed for user logic

  ------------------------------------------
  -- Signals for user logic slave model s/w accessible register example
  ------------------------------------------
  signal slv_reg0                       : std_logic_vector(0 to C_DWIDTH-1);
  signal slv_reg1                       : std_logic_vector(0 to C_DWIDTH-1);
  signal slv_reg2                       : std_logic_vector(0 to C_DWIDTH-1);
  signal slv_reg3                       : std_logic_vector(0 to C_DWIDTH-1);
  signal slv_reg_write_select           : std_logic_vector(0 to 3);
  signal slv_reg_read_select            : std_logic_vector(0 to 3);
  signal slv_ip2bus_data                : std_logic_vector(0 to C_DWIDTH-1);
  signal slv_read_ack                   : std_logic;
  signal slv_write_ack                  : std_logic;

begin

  --USER logic implementation added here

  ------------------------------------------
  -- Example code to read/write user logic slave model s/w accessible registers
  --
  -- Note:
  -- The example code presented here is to show you one way of reading/writing
  -- software accessible registers implemented in the user logic slave model.
  -- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
  -- to one software accessible register by the top level template. For example,
  -- if you have four 32 bit software accessible registers in the user logic, you
  -- are basically operating on the following memory mapped registers:
  --
  --    Bus2IP_WrCE or   Memory Mapped
  --       Bus2IP_RdCE   Register
  --            "1000"   C_BASEADDR + 0x0
  --            "0100"   C_BASEADDR + 0x4
  --            "0010"   C_BASEADDR + 0x8
  --            "0001"   C_BASEADDR + 0xC
  --
  ------------------------------------------
  slv_reg_write_select <= Bus2IP_WrCE(0 to 3);
  slv_reg_read_select  <= Bus2IP_RdCE(0 to 3);
  slv_write_ack        <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3);
  slv_read_ack         <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3);

  -- implement slave model register(s)
  SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
  begin

    if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
      if Bus2IP_Reset = '1' then
        slv_reg0 <= (others => '0');
        slv_reg1 <= (others => '0');
        slv_reg2 <= (others => '0');
        slv_reg3 <= (others => '0');
      else
        case slv_reg_write_select is
          when "1000" =>
            for byte_index in 0 to (C_DWIDTH/8)-1 loop
              if ( Bus2IP_BE(byte_index) = '1' ) then
                slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
              end if;
            end loop;
          when "0100" =>
            for byte_index in 0 to (C_DWIDTH/8)-1 loop
              if ( Bus2IP_BE(byte_index) = '1' ) then
                slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
              end if;
            end loop;
          when "0010" =>
            for byte_index in 0 to (C_DWIDTH/8)-1 loop
              if ( Bus2IP_BE(byte_index) = '1' ) then
                slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
              end if;
            end loop;
          when "0001" =>
            for byte_index in 0 to (C_DWIDTH/8)-1 loop
              if ( Bus2IP_BE(byte_index) = '1' ) then
                slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
              end if;
            end loop;
          when others => null;
        end case;
      end if;
    end if;

  end process SLAVE_REG_WRITE_PROC;

  -- implement slave model register read mux
  SLAVE_REG_READ_PROC : process( slv_reg_read_select, slv_reg0, slv_reg1, slv_reg2, slv_reg3 ) is
  begin

    case slv_reg_read_select is
      when "1000" => slv_ip2bus_data <= slv_reg0;
      when "0100" => slv_ip2bus_data <= slv_reg1;
      when "0010" => slv_ip2bus_data <= slv_reg2;
      when "0001" => slv_ip2bus_data <= slv_reg3;
      when others => slv_ip2bus_data <= (others => '0');
    end case;

  end process SLAVE_REG_READ_PROC;

  ------------------------------------------
  -- Example code to drive IP to Bus signals
  ------------------------------------------
  IP2Bus_Data        <= slv_ip2bus_data;

  IP2Bus_Ack         <= slv_write_ack or slv_read_ack;
  IP2Bus_Error       <= '0';
  IP2Bus_Retry       <= '0';
  IP2Bus_ToutSup     <= '0';

end IMP;

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Participant nc6
Participant
9,754 Views
Registered: ‎05-07-2009

Re: Create or Import IP Peripheral ---- HDL parser error detected

there is no syntax error or parser error in this file. I have created IPs before in EDK 9.1 CIP module and have found it error free. 

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Visitor mbspartan
Visitor
9,739 Views
Registered: ‎07-07-2009

Re: Create or Import IP Peripheral ---- HDL parser error detected

so why am i getting this error

 

SOME QUESTIONS FOR YOU, if you dont mind; 

 

is it because the Xilinx tutorial im using is for "EDK 9.1 MicroBlaze Tutorial in Virtex-4"?

 

Im just trying to get my hyperterminal working on my Spartan 3E board with 9.1 Tools, cant find alot of microblaze tutorials for 9.1 do you know where i can get these?

 

Also can i upgrade to 9.2 or will it cost?

 

 

 

 

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Participant nc6
Participant
9,692 Views
Registered: ‎05-07-2009

Re: Create or Import IP Peripheral ---- HDL parser error detected

no problem. the tutorial you are using is just fine. i suggest you redo the peripheral creation, and it shud solve the error. I did the periperhal creation by the manual (just to check) and it created fine.

 

upgrading to 9.2 doesnt make sense at this time and for the project you are trying to do now.

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Visitor mbspartan
Visitor
9,671 Views
Registered: ‎07-07-2009

Re: Create or Import IP Peripheral ---- HDL parser error detected

Ok, i will try that asap, thanks

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