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Critical Warning in PlanAhead

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Voyager
Posts: 277
Registered: ‎02-10-2012
Accepted Solution

Critical Warning in PlanAhead

Hello ,

 

I am creating a Zynq based design in PlanAhead 14.5 and there are 3 critical warnings which I am finding difficult to get rid off. They are produced because of the processing_system7_0_wrapper.ncf file. They are :

[Constraints 18-5] Cannot loc instance 'processing_system7_0_PS_PORB_IBUF' at site B5, Site location is not valid

[Constraints 18-5] Cannot loc instance 'processing_system7_0_PS_SRSTB_IBUF' at site C9, Site location is not valid

[Constraints 18-5] Cannot loc instance 'processing_system7_0_PS_CLK_IBUF' at site F7, Site location is not valid


My understanding was that the wrapper files are auto generated by the tools. Why does it produce an invalid side location and assign them as constraints ?

 

Regards

Arvind

 

 


Accepted Solutions
Xilinx Employee
Posts: 3,600
Registered: ‎08-02-2011

Re: Critical Warning in PlanAhead

This is coming from memory, so bear with me (I think I have it right though :) )

 

So these pins are dedicated PS pins and their 'loc' is fixed to the PS. Thus, UCF constraints for these pins are not useful from the tool's perspective. They don't go through the fabric at all.

 

Thus you can just ignore any messages about them. They are simply the result of using an FPGA tool for this type of device. As mentioned, it's fixed in vivado and these messages no longer appear.

www.xilinx.com

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Xilinx Employee
Posts: 3,600
Registered: ‎08-02-2011

Re: Critical Warning in PlanAhead

Hi Arvind,

You can ignore those warnings. They're supposed to be removed in a future version of the tools.
www.xilinx.com
Voyager
Posts: 277
Registered: ‎02-10-2012

Re: Critical Warning in PlanAhead

[ Edited ]

Thanks for the Reply bwiec.

 

Just one question. I went ahead with the design and I face many warnings related to these three pins . I ran a Report DRC after implementation and I get this warning :

 

3 out of 64 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. Problem ports: processing_system7_0_PS_SRSTB, processing_system7_0_PS_CLK, processing_system7_0_PS_PORB.

 

I was able to generate the bit stream file without setting the above mentioned property . I don't know how that worked. But my understanding was that these constraints are auto assigned by the tools but since it sees it as invalid sites , the above 3 signals are not constrained. And that is why its causing all these problems.

 

Can I ignore this issue ?

 

On another note I am not sure if this is related to the above problem or not I get these warnings in synthesis :

 

[Xst 528] Multi-source in Unit <processing_system7_0> on signal <PS_SRSTB>; this signal is connected to multiple drivers.
[Xst 528] Multi-source in Unit <processing_system7_0> on signal <PS_CLK>; this signal is connected to multiple drivers.

[Xst 528] Multi-source in Unit <processing_system7_0> on signal <PS_PORB>; this signal is connected to multiple drivers.


Since mine is a Hierarchical design i figured I might have connected the signal to another component by mistake. But I double checked and triple checked in the elaborate design for RTL analysis and there is no way its connected to multiple drivers. I thought this was some kind of a bug.

 

So I closed my design and made a new project with just the processor , ran the create the top HDL and started implementation. It still reports these warnings.! Am I doing something wrong ? 


Regards

Arvind

 

Xilinx Employee
Posts: 3,600
Registered: ‎08-02-2011

Re: Critical Warning in PlanAhead

This is coming from memory, so bear with me (I think I have it right though :) )

 

So these pins are dedicated PS pins and their 'loc' is fixed to the PS. Thus, UCF constraints for these pins are not useful from the tool's perspective. They don't go through the fabric at all.

 

Thus you can just ignore any messages about them. They are simply the result of using an FPGA tool for this type of device. As mentioned, it's fixed in vivado and these messages no longer appear.

www.xilinx.com
Voyager
Posts: 277
Registered: ‎02-10-2012

Re: Critical Warning in PlanAhead

Oh thats such a relief! Thank you so much for the information. That cleares one problem of my head. :)

 

Regards

Arvind

Observer
Posts: 35
Registered: ‎10-18-2013

Re: Critical Warning in PlanAhead

Is it OK to comment out those 3 lines in the wrapper ncf file to get rid of all the warnings?