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gatorbite5
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Registered: ‎05-11-2012

Custom IP: FIFO Replacement

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I created a Custom IP that is an AXI_Burst Core with AXI Master and AXI Slave interfaces.  USER_Logic file show that it contains a FIFO with a depth of 128 beats.  I have tried modifying the value of 128 to 512, and then rescanning the User Repositories to add the change, but it seems to have no change in the functionality of my FIFO.  Is there a way that from the ISE project for the VHDL File in my Custom IP, that I can swap out the Xilinx Provided FIFO with a FIFO I create with the CoreGEN Wizard in ISE...and then be able to rescan the User Repositories to add the change back into my XPS Design?

 

Thanks in advance for the help!

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hgleamon1
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Registered: ‎11-14-2011

You need the actual .ngc in the netlist folder and the name of the .ngc in the BBD file. the syntax is simply the name of the file, including the .ngc extension.

 

After that, you should be OK.

 

Note: if you don't have a netlist folder in your pcore directory, simply create one.

 

 -- edit

 

A BBD file is created if you write in the pcore MPD that the pcore uses a mixed design (HDL and NGC). It is only a text file, albeit with the extension .bbd, and can easily be created. This raises another point. You must edit your pcore MPD (or check, at least) to ensure that the OPTION STYLE is set to MIXED.

 

 -- end edit

 

Regards,

 

Howard

 

----------
"That which we must learn to do, we learn by doing." - Aristotle

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Anonymous
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when you create the ip in the cip wizard, you have the I option to create a ISE project.

you should open this and add the fifo from coregen and instanciste this into the user logic.

you can ruin a simulation to test the functionality. 

 

Once everything is tested, you will have to add the library to the poa file in the data folder in 

your custom ip directory. This tells the tool the order to compile the hdl code.

 

 

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gatorbite5
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stephenm,

 

Thanks for your quick reply!  I enabled that option when I created the peripheral and have added the FIFO I want from CoreGen to that project.  

 

However, I don't know how to add the library to the poa file inthe data folder that you are talking about.  What library do I add?  Is it just the folder for the files created by CoreGen?

 

Thanks again for your help!

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hgleamon1
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You need to tell the tools the location of the FIFO HDL. A quick look at your custom IP PAO file will give the idea of the format but it should be something like this:

 

lib <your_ip_name> <relative_path_to_fifo/fifo_name> [vhdl | verilog]

 

Note that the location of the FIFO HDL is a RELATIVE path. You may have to go backwards /../../folder_name, for example.

 

Interestingly, you can specify that a file is for simulation only - very likely for coregen FIFOs where the NGC will sit under the netlist drectory. In this case, you can specify simlib instead of lib

 

Also, remember to specify the correct FIFO NGC in the BBD!

 

Regards,

 

Howard

 

----------
"That which we must learn to do, we learn by doing." - Aristotle
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gatorbite5
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hgleamon1,

 

Thanks for your reply!  When I created the FIFO in the ISE Project, the files were placed at <ip_name>\devl\projnav.  I tried to set this as the path as you stated in your repsonse, but when I rescan the user repositories in XPS, I am told that AXI_Master_FIFO.v is not found, yet I see the file in the directory.

 

I then decided to copy the .v file to <ip_name>\vhd\verilog and sedt the path as seen below:

lib <ip_name> AXI_Master_FIFO verilog

 

Doing this gives me an error when I attempt to generate the bitstream  saying that AXI_Master_FIFO is not a component.

 

Any ideas as to what I am doing wrong? Am I not using all of the files that I should be for the PAO file?

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hgleamon1
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Hmm, might be a difference if you use a backslash (\) rather than a forward slash (/). You have quoted backslashes, so try forward slashes.

 

Not sure about the other problem as I often copy files into the relevant HDL directory for my designs. Can you attach your PAO?

 

Regards,

 

Howard

 

----------
"That which we must learn to do, we learn by doing." - Aristotle
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gatorbite5
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hgleamon1,

 

I had previously tried the difference between forward slash and backslash, but saw no difference.

 

I went into the ISE Project and changed the default language from Verilog to VHDL and recreated the FIFO with the files placed in the <ip_name>\vhd\vhdl folder.  Now my project starts to create the bitstream, but errors out from a pin misspelling, or so it says, but I can't find any differences...so I am looking into this error now.

 

Thanks for your help!

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gatorbite5
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hgleamon1,

 

Using the ISE Project, I attempted to Generate the Programming File to get more information about the misspelling error, but the only error was due to not having a .ucf file in the project.  Therefore, I assume that my connections in the User_Logic file with my custom FIFO is correct.  I have attached the User_Logic.vhd file, the .pao file, and the VHDL Instantiation Template for the FIFO I am trying to add (.vho file).  If you would please look over them and see if you can find what I am doing wrong, I would appreciate it.  The files are all in the .zip folder attached titled "axi_master_v2_1_0.zip"

 

Assuming that there is nothing wrong with my files, all I should have to do is Rescan the User Repositories and then start creating the bitstream, correct?

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hgleamon1
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At first glance - your declaration of the FIFO in the PAO should come BEFORE the user logic. The order is hierarchical. Probably why the tools state it can't be found.

 

Regards,

 

Howard

 

----------
"That which we must learn to do, we learn by doing." - Aristotle
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gatorbite5
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hgleamon1,

 

I swapped the FIFO declaration in the PAO file to come before the User_Logic declaration as you suggested, but I still get the pin misspelling error.  Below is the full error message.  

 

ERROR:NgdBuild:604 - logical block

'axi_master_0/axi_master_0/USER_LOGIC_I/FIFO_32x1024' with type 'Master_FIFO'
could not be resolved. A pin name misspelling can cause this, a missing edif
or ngc file, case mismatch between the block name and the edif or ngc file
name, or the misspelling of a type name. Symbol 'Master_FIFO' is not
supported in target 'kintex7'.

 

Any ideas about what is causing it?

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hgleamon1
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HDL files for coregen parts are declared in the PAO file for SIMULATION ONLY. For synthesis and PAR, the underlying .ngc must be placed in the netlist directory and the corresponding declaration made in the BBD file.

 

Have you declared the Master FIFO .ngc in the bbd file in the data directory?

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"That which we must learn to do, we learn by doing." - Aristotle
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gatorbite5
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hgleamon1,

 

No I haven't.  I appologize because this type of swapping is very new to me.  Is declaring the Master FIFO .ngc in the bbd all I need to do to build the project and be able to export to SDK for software development/testing?  Is it a similar process to what I did for declaring the Master FIFO in the PAO file?

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gatorbite5
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I just looked through my project folder and don't even see any .bbd files.  Are these something that I need to create within XPS or how do I create this file?

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hgleamon1
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You need the actual .ngc in the netlist folder and the name of the .ngc in the BBD file. the syntax is simply the name of the file, including the .ngc extension.

 

After that, you should be OK.

 

Note: if you don't have a netlist folder in your pcore directory, simply create one.

 

 -- edit

 

A BBD file is created if you write in the pcore MPD that the pcore uses a mixed design (HDL and NGC). It is only a text file, albeit with the extension .bbd, and can easily be created. This raises another point. You must edit your pcore MPD (or check, at least) to ensure that the OPTION STYLE is set to MIXED.

 

 -- end edit

 

Regards,

 

Howard

 

----------
"That which we must learn to do, we learn by doing." - Aristotle

View solution in original post

gatorbite5
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hgleamon1,

 

So all I should have to do is create the subfolder "pcores\netlist" and add the .ngc file for the Master_FIFO to that folder by copy and paste.  Then I should also edit the  .mpd for the IP so say "OPTION STYLE = MIXED" so that a .bbd file is created for me to add the name of the .ngc file to?  I'm jsut trying to understand this before I attempt it and screw something up with my design since this is new for me.  Thanks again for your help!

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gatorbite5
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Do I need to add the .ngc file to the netlist.lst file found in the implementation directory?

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hgleamon1
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The netlist directory will sit under YOUR pcore - axi whatever it was. In the same folder as the data and hdl directories.

 

I don't think you need to worry about the netlist.lst file in implementation.

 

I don't know if the BBD file (and netlist directory, for that matter) will be created for you now that your pcore already exists. If you edit the MPD and rescan in XPS, you will see whether the file is there or not. If not, create it.

 

If you are unsure of what may happen to your design, copy it all in to .zip file NOW so you can go back later on if you have to.

 

Regards,

 

Howard

 

----------
"That which we must learn to do, we learn by doing." - Aristotle
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gatorbite5
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hgleamon1,

 

Thanks for your help.  I made those changes with the .ngc file and .bbd file that you suggested and it worked perfectly.  Thanks again for your time and effort!

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markzak
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Just to close the loop on this thread, two points need to be made.

 

1) The string to add to your .mpd file is actually "OPTION STYLE = MIX"

2) The BBD file does not get generated automatically.  You need to create it with a text editor and locate it in your /Data directory. it should have the exact same named as both your .MPD and .PAO files, albeit with a .BBD extension.

 

 

Here's the official word on this.

http://www.xilinx.com/support/answers/22882.htm (What should I do to instantiate a netlist core in my custom peripheral?)

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