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Contributor
Contributor
5,470 Views
Registered: ‎03-13-2008

Custom IP peripherial with core Generator

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Hello,

I have built my custom IP without using any core generator components. and the system run properly.

But when i included any port map component that i generated from CORE Genarator, this error rise.

"

ERROR:NgdBuild:604 - logical block 'fifo_ip_0/fifo_ip_0/USER_LOGIC_I/FiFo_inst'
   with type 'FIFO_core' could not be resolved. A pin name misspelling can cause
   this, a missing edif or ngc file, or the misspelling of a type name. Symbol
   'FIFO_core' is not supported in target 'virtex4'.

 

"

 

What should i do?

 

 

Thank you in advanced.

 

Best Regards.
Hamzah A. Abdel-Aziz
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Contributor
Contributor
6,438 Views
Registered: ‎03-13-2008

It is seem to be a joke.

when my evaluation duration expired. and i registered my EDK and ISE with full version Reg ID,  the error does not appear. and bit file was created successfully.

:smileytongue:

 

 

 

Message Edited by hamzah.aaaa on 04-13-2009 06:27 AM
Best Regards.
Hamzah A. Abdel-Aziz

View solution in original post

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Xilinx Employee
Xilinx Employee
5,455 Views
Registered: ‎08-13-2007

Hamzah,

 

You may find this useful:

http://forums.xilinx.com/xlnx/board/message?board.id=EDK&message.id=5631 (Put Coregen component into EDK library?)

 

Cheers,

bt

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Scholar
Scholar
5,438 Views
Registered: ‎04-07-2008

Some checks you should do:

 

under the pcores directory and under the directory for your core there is four directories:

data, devl, hdl, netlist.

 

under data open the bbd file and see if there is a line that looks like this:

 

 

##############################################################################

## Filename: C:\XXX\SLOW_FIFO_JUL29\pcores/tx_v1_01_a/data/tx_v2_1_0.bbd

## Description: Black Box Definition

## Date: Tue Jul 29 09:24:30 2008 (by Create and Import Peripheral Wizard)

##############################################################################

Files

################################################################################

writefifo_2k_PE_v4_3.ngc,burst_fifo_1k_vr4_3.ngc

 

make sure that the ngc files are listed in this file.

 

 

check you MPD File in My case:

 

 

###################################################################

##

## Name : tx

## Desc : Microprocessor Peripheral Description

## : Automatically generated by PsfUtility

##

###################################################################

BEGIN tx

## Peripheral Options

OPTION IPTYPE = PERIPHERAL

OPTION IMP_NETLIST = TRUE

OPTION HDL = MIXED

OPTION ARCH_SUPPORT_MAP = (OTHERS=DEVELOPMENT)

OPTION IP_GROUP = MICROBLAZE:PPC:USER

OPTION STYLE = MIX

OPTION RUN_NGCBUILD = TRUE

 

 

I think that Option

 

OPTION IMP_NETLIST = TRUE

and

OPTION STYLE = MIX

 

for cores that include ngc's

 

I have in my case mixed VHDL and Verilog so in my case I also need

OPTION HDL = MIXED  << for VHDL and Verilog

 

 

Also under the Netlist directory place the ngc file if it is not in the directory

 

 

 

 

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Contributor
Contributor
5,353 Views
Registered: ‎03-13-2008

timpe/ golson

 

Thank you very much for your reply.

Acctually i did this before writing this post.

 

but the error still exist.

 

Thanks

Best Regards.
Hamzah A. Abdel-Aziz
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Highlighted
Contributor
Contributor
6,439 Views
Registered: ‎03-13-2008

It is seem to be a joke.

when my evaluation duration expired. and i registered my EDK and ISE with full version Reg ID,  the error does not appear. and bit file was created successfully.

:smileytongue:

 

 

 

Message Edited by hamzah.aaaa on 04-13-2009 06:27 AM
Best Regards.
Hamzah A. Abdel-Aziz

View solution in original post

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