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fred@adapteva
Observer
Observer
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Registered: ‎07-23-2014

Custom interface: Multiple slaves / masters?

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Greetings,

 

In Vivado block diagram designs I've been happily creating custom interfaces, significantly cleaning up the diagrams and I'm sure reducing errors, nice!  However I'm puzzled about the entries for # of masters / # of slaves.  Even if I set the # of slaves > 1 I don't seem to be able to connect more than one at a time to any master.  I also don't seem to be able to set it to -1 which I expect to allow any number of slave connections?

 

Here's my scenario, though I can think of others:  I have a set of configuration and status registers, groups of bits that control the behavior of various blocks in the system and report on status from different blocks.  Some of the control bits are dedicated to particular blocks but others are shared among more than one.  The status bits on the other hand are never shared as they are inputs to my CSR block, but they are divided between the slaves.

 

I'd like to define one custom interface that has all the status & control register bits on it, with my CSR block acting as a single master and the other blocks all being slaves on the same CSR bus.  Something like this:

 

Master:
output [] global_enables;
output [] a_control;
output [] b_control;
input [] a_status;
input [] b_status;

Slave A:
input [] global_enables;
input [] a_control;
output [] a_status;

Slave B:
input [] global_enables;
input [] b_control;
output [] b_status;

 Can I do this with a single interface?  I tried making all the ports optional on the slave side, and set # of slaves to 2, but when I'm creating the block diagram once I connect one pair I can no longer connect the other.  If this is not the purpose of the # of slaves parameter I can't think why it's there.

 

Cheers.

 

 

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swolf
Xilinx Employee
Xilinx Employee
12,901 Views
Registered: ‎07-09-2013

Hi Fred,

 

The difficulty is what to do with the handshaking signals and outputs from the slave in an FPGA.  In hardware you could create tristates and pullups and what not to wire together a "bus" and somehow encode an ability to avoid conflicts.  Its hard to do that in an FPGA: it would look like the outpus from all the slaves are conflicting with each other if you just tried to wire them together.  Something is needed to combine these signals (like a mux to pick only one of them).

 

Because of this, IPI is essentially a point to point interface connection tool and you'd need some "interconnect" between the master and mutliple slaves to control things.

 

In the packger, the "number of slaves" is a somewhat vestigial hold over from the IP-XACT definition.  The only relevant numbers there for IPI are 0 and anything else.

 

 

As far as creating an interconnect or mux like IP with a variable number of (slave) interfaces, you can start by

1) packaging up HDL with a maximum number of ports

2) add a generic/parameter to indicate the number of slaves

3) use enablement expressions on the interfaces and ports to hide the interface

  - find the interface in the ports & interfaces tab, double click on it, indicate it is optional and enter the expression

bus_enablement_gui.png

 

In this example, the tcl issued from it is

set_property enablement_dependency {$num_slaves > 0} [ipx::get_bus_interfaces S00_AXI -of_objects [ipx::current_core]]

You might want to use TCL to loop through the interfaces and change the literal 0 apprpriately for each interface.

 

 

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muzaffer
Teacher
Teacher
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Registered: ‎03-31-2012
This is what AXI interconnect does. You can configure it to have arbitrary number of (within reason) slaves and masters. It might help to read the tcl file and the xlm file for the description and gui dialog for the axi interconnect to figure out how it is done.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
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fred@adapteva
Observer
Observer
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Registered: ‎07-23-2014

@muzaffer wrote:
This is what AXI interconnect does. You can configure it to have arbitrary number of (within reason) slaves and masters. 

That's quite different, the AXI interconnect is a module that can implement a number of slaves & masters, but each interface, each "wire" on the diagram, still only has one master and one slave.  It would be easy to write a module that has one of my custom CSR slaves and an arbitrary number of masters (in fact I've already done this to work around the problem until there is a solution), but I think it should be possible to do this by directly connecting one master to multiple slaves.  If it's not possible then I don't understand what the "Max. Slaves" and "Max Masters" properties are for.  Perhaps "reserved for future use?"

 

I'm not expert enough to write a module that has a variable number of ports, so I had to add as many as I could imagine using.  There seems to be some support in the packager for configurable modules, can anyone point me to the documentation for that feature?  I haven't seen it but I know I still have plenty to learn.  If the only way is to read the tcl / xlm files I'll probably wait until it becomes a supported & documented feature.  Or until I really really need it.

 

Cheers.

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swolf
Xilinx Employee
Xilinx Employee
12,902 Views
Registered: ‎07-09-2013

Hi Fred,

 

The difficulty is what to do with the handshaking signals and outputs from the slave in an FPGA.  In hardware you could create tristates and pullups and what not to wire together a "bus" and somehow encode an ability to avoid conflicts.  Its hard to do that in an FPGA: it would look like the outpus from all the slaves are conflicting with each other if you just tried to wire them together.  Something is needed to combine these signals (like a mux to pick only one of them).

 

Because of this, IPI is essentially a point to point interface connection tool and you'd need some "interconnect" between the master and mutliple slaves to control things.

 

In the packger, the "number of slaves" is a somewhat vestigial hold over from the IP-XACT definition.  The only relevant numbers there for IPI are 0 and anything else.

 

 

As far as creating an interconnect or mux like IP with a variable number of (slave) interfaces, you can start by

1) packaging up HDL with a maximum number of ports

2) add a generic/parameter to indicate the number of slaves

3) use enablement expressions on the interfaces and ports to hide the interface

  - find the interface in the ports & interfaces tab, double click on it, indicate it is optional and enter the expression

bus_enablement_gui.png

 

In this example, the tcl issued from it is

set_property enablement_dependency {$num_slaves > 0} [ipx::get_bus_interfaces S00_AXI -of_objects [ipx::current_core]]

You might want to use TCL to loop through the interfaces and change the literal 0 apprpriately for each interface.

 

 

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fred@adapteva
Observer
Observer
8,273 Views
Registered: ‎07-23-2014

@swolf wrote:

The difficulty is what to do with the handshaking signals and outputs from the slave in an FPGA.  In hardware you could create tristates and pullups and what not to wire together a "bus" and somehow encode an ability to avoid conflicts.  Its hard to do that in an FPGA: it would look like the outpus from all the slaves are conflicting with each other if you just tried to wire them together.  Something is needed to combine these signals (like a mux to pick only one of them).


 

Considering all the very clever things the tools do now this one seems trivial.  Leave it up to the user to only populate one driver for each "return" signal, and flag an error if this is violated.  Done.  The BD editor has all the info it needs to check this.  If you look at my example it uses optional ports in the return direction, and it was up to me to make sure only one slave (at most) had each signal.  This is already done with basic signals and arrays, I can connect them from one source to multiple sinks no problem, but even if my interface is only unidirectional I can't connect it to multiple slaves.  Even that would be a useful feature.   

 


@swolf wrote:

Because of this, IPI is essentially a point to point interface connection tool and you'd need some "interconnect" between the master and mutliple slaves to control things.


 Except that it works for simple signals, it's only interfaces that are restricted.

 


@swolf wrote:

In the packger, the "number of slaves" is a somewhat vestigial hold over from the IP-XACT definition.  The only relevant numbers there for IPI are 0 and anything else.


 

OK, that's the answer, too bad.  I'm curious, do you mean "the only relevant numbers are 1 and nothing else"?  "0 and anything else" sounds like anything is relevant. 

 

Thanks for the info on creating customizable modules, IMHO that's much more sophisticated than allowing interfaces to connect to multiple slaves!  ;-)  I was looking for something clever in how the verilog was handled, but I understand it's purely a cosmetic thing regarding how many ports show up on the module.

 

Cheers,

  Fred

 

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elod.gyorgy
Adventurer
Adventurer
8,196 Views
Registered: ‎01-23-2012

I hit the same roadblock while defining my custom interfaces. The max. masters and slaves parameters induced me into thinking that it would be possible to wire interfaces to multiple slaves. I don't understand why it couldn't be done for interfaces where all the signals are either input or output depending on the interface role.

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