Customization of the addressable memory size when using the "Create or Import peripheral" wizard

[dtheodor]

Hello everyone,

I am using the EDK and Xilinx 9.2. I use the "Create or import peripheral" wizard to design a custom SPLB v4.6 design. I want to use also an addressable memory space, so I select 1 memory space from the wizard. However, there is no  way to customize the size that it will be addressable. By selecting as native data width 64 bits, the wizard always generates a 256x64 bits memory block per addressable space. That is, if I choose 2 addressable spaces, then the wizard will generate 2 256x64 bits memory blocks. Is there any way to change the size of the memories?

Thank you very much!

kind regards,

dhteodor

[amego83]

Hi, 

Have you tried to check the document of the IPIF document. may be you could find some informations.

About the your new PLB bus and the SPLB of your custom IP could you show a picture of that.

Good Luck 

[xiaofeip_dup · Accepted solution]

Hi dhteodor,

It's been a while since I looked into it, but  I remember that the size of the memory depends on how many bits of the address being decoded. 

Check out the example code and look for the address signals from the IPIF, you should be able to find the code.

-Felix

[dtheodor]

Hello all,

Thank you very much your replies and suggestions. Indeed the automatically generated code provides the address signals, so it should be feasible to change the size of the addressable memory.

Based on this, I believe one nice addition to the wizard would be to allow the selection of the size for the addressable memory and not only how many the user wants to instantiate.

Once again thank you very much for your help.

Kind regards,

dtheodor