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heedaf
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Registered: ‎06-25-2008

DDR Controller for XPS

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I noticed that the DDR controller is in both Verilog and VHDL but I guess it is being compiled as Verilog.  Is there anyway to force it to load the VHDL file instead?

Thanks,

DeWayne

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Chadn_na
Xilinx Employee
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Registered: ‎08-15-2007
If you are using MPMC, there is not a VHDL version and verilog version.  The core is mixed language so you will not be able to simulate it with only a VHDL license. 

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rickys
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Registered: ‎08-01-2007

In regards to the core mpmc_v4_02_a, both verilog and vhdl are used in this core.

 

The compile list can be found at

<EDK>\hw\XilinxProcessorIPLib\pcores\mpmc_v4_02_a\data\mpmc_v2_1_0.pao

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heedaf
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I'm trying to use Modelsim PE student addition and EDK is compiling the Verilog version and I need it to use the VHDL version since the student addition won't do both.

Thanks,

DeWayne

Message Edited by heedaf on 08-19-2008 08:40 AM
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Chadn_na
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If you are using MPMC, there is not a VHDL version and verilog version.  The core is mixed language so you will not be able to simulate it with only a VHDL license. 

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alexsvet
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chadn wrote:
If you are using MPMC, there is not a VHDL version and verilog version.  The core is mixed language so you will not be able to simulate it with only a VHDL license. 

So, if I understand this right, there is not possibility to simulate a design with MPMC or DDR(2) controller created with MIG with any free version of ModelSim, XE or PE?

 

Aleš

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heedaf
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XE isn't compatible with EDK and the student version of PE will not do both VHDL and Verilog.  Since MPMC is a mixed language it will not work.

DeWayne

Message Edited by heedaf on 08-20-2008 02:41 PM
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alexsvet
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heedaf wrote:

XE isn't compatible with XPS and the student version of PE will not do both VHDL and Verilog.  Since MPMC is a mixed language it will not work.

DeWayne


So the following message is misleading:

 

#######################################################
#                                                                                                                     #
# This executes the ModelSim in batch mode, runs sim.do file and simulate the design.     #
# This sim.exe has been verified on ModelSim PE, ModelSim SE and ModelSim XE             #
# versions. You should provide unisim and unisims_ver libraries paths in order                  #
# to compile Xilinx primitives used in design. You can skip by pressing "Enter"                  #
# if libraries are internally mapped through modelsim.ini file. After the                             #
# simulation is run a log file sim_log.txt is generated that contains all                              #
# errors, warnings, violations and memory mode register details. Mode Registers             #
# may not be present for all designs.                                                                     #
#                                                                                                                   #
######################################################

 

This message is generated by running sim.exe, which was generated in simulation folder with coregen for MIG core...

I do not understand what the message is trying to say with "This sim.exe has been verified on ModelSim PE, ModelSim SE and ModelSim XE versions."

But actually we can not simulate this DDR memory controller with XE version...

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heedaf
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Student addition of PE won't do mixed files so the MPMC that is used with EDK won't work.  PE and SE should work fine.  XE is not compatible with EDK but it should simulate with IDE if that is what your are asking.

Message Edited by heedaf on 08-20-2008 02:40 PM
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