DDR DQ(S) signals hi-Z in simulation

Posts: 70
Registered: ‎03-27-2009

DDR DQ(S) signals hi-Z in simulation

I am using EDK9.2.02 and Spartan3E 1600e dev brd, I quickly created a edk microblaze design with only rs232 and mpmc ddr in order to see the activities on ddr dq and dqs, first I downloaded the design to s3e 1600e brd and from hyperterminal I have seen memory test pass which is expected, then I generated  simulation HDL files and test bench and hooked-up the memory model from micron in my system_tb.vhd and add compile command in, then invoke modelsim se 6.2b run for 1 ms, from the wave window, I saw signal MPMC_initDone went '1' a bit after 200 us which is good, however, the DDR_DQ and DDR_DQS were constant 'Z', I don't know if there is anything I am missing, pls advise.

here is the steps I did for simulation:

1)Project -> Project Options -> HDL and Simulation tab, tick 'Generate test bench template'.

2)Simulation -> Generate simulation HDL Files.

3)In system_tb.vhd, declare ddr.v (from Micron) using vhdl syntax and hook it up with signlas from edk system.

4)copy micron ddr model ddr.v and related files to project\simulation\behavioral.

5) in, add "vlog -incr -work work +define+x16 +define+FULL_MEM +define+sg6T "ddr.v" " before testbench compile command.

6)invoke modelsim, execute do, then type C,S,W, there is no error or warnings when testbench was compiled.

7) check wave window.



Posts: 70
Registered: ‎03-27-2009

Re: DDR DQ(S) signals hi-Z in simulation

stii nobody gave a shout???
Posts: 6
Registered: ‎11-01-2008

Re: DDR DQ(S) signals hi-Z in simulation

[ Edited ]



They are supposed to be Hi-Z when idle. DQ and DQS are inout signals to allow the DDR_controller to drive them when writing and the DDR_chip when reading.


If you issue a READ_CMD, DQS will start toggling if initialization was successful and everything went ok.

DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs.



Tools: ISE 10.1 SP3, ISim 10.1.


I'm developing a DDR controller for the SP31600-StarterKit and I'm using the Micron DDR model 46v32m16 (the one provided with MIG) and writing operations happen to succeed but for every read operation DQ[15:0] appears as XXXX, autorefresh and precharge are already taken care of.

Does anybody knows if it's an issue with the model or with ISim?



Message Edited by santiagordgz on 05-11-2009 02:36 PM
Posts: 3
Registered: ‎02-09-2011

Re: DDR DQ(S) signals hi-Z in simulation

Similar problem, but a little different.


In ISE 13.4, simulating with ISIM, DDR2 controller wrapped in MPMC.  Device = Spartan 6.


DQS and DQS_N signals are X from the beginning of time and never change.  Tracing down the hierarchy I see that they are driven by 2 primitives inside the controller: an iobuf and pulldown.  The pulldown is the one driving 'X'.  The iobuf has legal, non-Z inputs on its I and T ports and during (attempted) initialization when T toggles, the X on the net does not change.


This is a VHDL design.


I have done this before on another project with a Verilog top-level design and it worked fine!  I even went back and re-ran my old simulation to see for certain and there was no similar problem.


Things I've tried:

 - Run with and without DDR memory model in testbench

 - Run with and without additional "PULLDOWN" in the testbench

 - Run fuse specifying --timescape 1ps/1ps --override_timeunit and --override_timeprecision


None of these have any effect.