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barrygmoss
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Registered: ‎03-20-2018

DDR Memory Test on the Zynq MPSoC ZCU102

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I'm trying to create a simple DDR memory test for a ZCU102 using Vivado/SDK 2018.3

I created a bare-bones PS design in Vivado using the IP Integrator and using the board presets, generated a bitfile, exported hardware and launched SDK. 

In SDK, I added a new application project using the FSBL template, and added application project with the "Zynq MP DRAM tests" template. I generated a bootimage (FSBL, followed by the bitfile and the mem_test application elf file), programmed the flash successfully, switched SW6 to boot from the QSPI.

Unfortunately, this is where everything fails. The INIT_B LED stays red and the PS_ERROR also lights red. On the UART connection I see the following in my terminal:

MP First Stage Boot Loader
Release 2018.3 Jan 18 2019 - 12:22:47
Xilinx Zynq MP First S▒Xilinx Zynq MP First S▒Xilinx Zynq MP First S

Any suggestions? This seemed like a really straight forward test project (BTW, Hello World works on this board and we've run other projects on the board, so I doubt there is any kind of hardware failure). 

 (Edit--there was a cut and paste error in the title, which has now been corrected). 

 

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panantra
Xilinx Employee
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Registered: ‎06-13-2018

Hello @barrygmoss :

@bkzshabbaz understanding is correct here.
 
This DDR memory test issue occurs because, in order to test the entire DRAM, the PS DDR-specific test linker script is intended to be run from OCM, where the FSBL loading also exists in OCM. The FSBL is unable to overwrite itself with the DRAM test.
 
So, it is recommended to run the PS DRAM memory test from JTAG.
This is applicable to all Zynq US+MPSOC devices.
 
 
Thanks,
Priyanka
 
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ibaie
Xilinx Employee
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Registered: ‎10-06-2016

Hi @barrygmoss,

When you say hello world example works do you mean that works with a boot image or launching through the debugger? I would suggest also for the DDR test application to first of all try to execute it through the debugger rather than with a boot image.

Regards


Ibai
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barrygmoss
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Registered: ‎03-20-2018

I was trying to use a boot image, but I'll try switching to a debugger. --Barry

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bkzshabbaz
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Registered: ‎01-25-2018

Sounds like you're trying to do exactly what this person is doing:

https://forums.xilinx.com/t5/Embedded-Linux/SDK-Memory-Tests-Zynq-DRAM-Tests/td-p/897707

I've responded to that post with what I think is happening.

Long story short: The DRAM test template is supposed to run out of OCM.  Unfortunately, the FSBL also runs out of OCM, and may be preventing itself from overwriting.

Hello world works because it runs out of DDR.

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panantra
Xilinx Employee
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Registered: ‎06-13-2018

Hello @barrygmoss :

@bkzshabbaz understanding is correct here.
 
This DDR memory test issue occurs because, in order to test the entire DRAM, the PS DDR-specific test linker script is intended to be run from OCM, where the FSBL loading also exists in OCM. The FSBL is unable to overwrite itself with the DRAM test.
 
So, it is recommended to run the PS DRAM memory test from JTAG.
This is applicable to all Zynq US+MPSOC devices.
 
 
Thanks,
Priyanka
 
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