01-07-2010 11:21 PM
I have a simple problem that I would have thought is easy to solve, but very little on this forum gives any help.
I have a system V4FX20 + MPMC + MT46V32M16 DDR Memory (A similar setup to a V4FX12 MiniModule).
I downloaded the MT46V memory model from Micron in Verilog, made a XPS IP core out of it and added it to EDK.
1. Has anyone done this before?, and if so how are the IO ports handled. EDK spits an error saying the ports must be connected externally from the MPMC (not internally as would be the case with a simulation DDR). Do I need to re-write the MPMC core to meet the _I, _O and _T requirements?
2. How do you init the data from a .elf file into the DDR? I have seen XAPP436, but (surprise) the links to the design files are moved.
Any help would be great, thanks.
01-07-2010 11:42 PM
You should not add the memory model to the XPS design. Instead create the simulation model of your FPGA design (processor, MPMC and whatever IP core you need) within EDK; then write a test-bench that includes your top level (system.vhd) and the DDR memory model and simulate this file.
01-08-2010 06:19 AM
I think xapp1003 would give you idea about the file system required to simulate MPMC design with EDK and required simulator, though it is implemented for PPC440.
You can instantiate the simulation model of memory in the test bench created by EDK and then go ahead to simuatle your design.
01-09-2010 06:41 PM
Thanks to all that replied to me.
I researched the two following links
I also used XAPP1003 for the memory generation files.
I will post the solution later on, but for now I have another question:
I wrote a basic bootloader that resides in BRAM that will vector the PPC405 to the start of DDR after reset, BUT:
How do I delay the PPC executing code from BlockRAM until the MPMC has set its InitDone pin.??