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Visitor durano
Visitor
12,488 Views
Registered: ‎09-17-2007

DDR on custom board with EDK 8.1.02i

Hi,

I'm experiance some trouble when using the opb_ddr controller in EDK 8.1.02i along with ISE 8.1.03i.

I'm using an custom made board. On the board there is an Virtex II Pro, RS-232, Kingston SODIMM 1GB SDRAM (KVR333X64SC25/1G) and some other items. The board has an system clock of 30.72MHz.

When I create project for my board I use an custom made .xbd file which can be found below.

The problem is that the DDR memory is only readable in some of the projects that are made.

For example if I create a project using an Microblaze at 92.16MHz, an UART and the DDR memory. This gives an successful output from the testmemory application.

But if for example I create an new project using the same but adds an ethernet_lite. The system fails the memory test.

Sometimes the bigger projects also works. But as the system becomes larger it seems it fails more and more frekvently. I have locked the DCM's and it gives the same result that sometimes it works but not always.

I dont think its the DDR memory that is the problem as if I get a bit file that works it works flawlessly all the time. I tried non cached, cached and direct linked memory. But they all give the same result that it works sometimes but not all.

I was thinking that it might be a problem with delays internally in the FPGA as the DDR clock signals are fairly sensitive. But I haven't been able to figure ot what could couse the problem.

I can also note that the board has been used in an FPGA design without EDK and there using an other DDR core with no problem at all. I've also tested building projects to an Spartan 3E starterkit and thoose works everytime.

Here below you can find the .xbd file I'm using. You can see that I'm not using the whole 1GB of the memory but only the first 512MB.

I also adds manually constraints to lock the DCM's etc to the constraintfile in XPS, as can bee seen below aswell.

I would be very happy if I could get some help figuring out what the problem might be.

Thanks in advice

============================================
ATTRIBUTE VENDOR = MyBoard
ATTRIBUTE SPEC_URL = www.board.com
ATTRIBUTE CONTACT_INFO_URL=http://www.board.com
ATTRIBUTE NAME = Board1


ATTRIBUTE REVISION = F
ATTRIBUTE DESC = Board1 Revision F
ATTRIBUTE LONG_DESC = 'This is my board'

BEGIN IO_INTERFACE
ATTRIBUTE IOTYPE = XIL_CLOCK_V1
ATTRIBUTE INSTANCE =clk_100
PARAMETER CLK_FREQ =30720000, IO_IS=clk_freq, RANGE=(30720000)
PORT USER_SYS_CLK = CLK_100MHZ_OSC, IO_IS=ext_clk
END

BEGIN IO_INTERFACE
ATTRIBUTE IOTYPE = XIL_RESET_V1
ATTRIBUTE INSTANCE =rst_0
PARAMETER RST_POLARITY = 0, IO_IS=polarity, VALUE_NOTE=Active LOW
# push button 1 is dedicated to system reset.
PORT FPGA.RESET = CONN_FPGA.RESET, IO_IS=ext_rst
END

BEGIN IO_INTERFACE
ATTRIBUTE IOTYPE = XIL_UART_V1
ATTRIBUTE INSTANCE=RS232_DCE
PORT RXD_DCE = CONN_RXD_DCE, IO_IS=serial_in
PORT TXD_DCE = CONN_TXD_DCE, IO_IS=serial_out, INITIALVAL = GND
END

BEGIN IO_INTERFACE
ATTRIBUTE IOTYPE = XIL_ETHERNET_V1
ATTRIBUTE INSTANCE = Ethernet_MAC
PORT TXER = CONN_JX1_A19, IO_IS=ETH_TXER
PORT TXC = CONN_JX1_A35, IO_IS=ETH_TXC
PORT RXC = CONN_JX1_A33, IO_IS=ETH_RXC
PORT CRS = CONN_JX1_B25, IO_IS=ETH_CRS
PORT RXDV = CONN_JX1_A17, IO_IS=ETH_RXDV
PORT RXD0 = CONN_JX1_B17, IO_IS = ETH_RXD[0]
PORT RXD1 = CONN_JX1_B16, IO_IS = ETH_RXD[1]
PORT RXD2 = CONN_JX1_A15, IO_IS = ETH_RXD[2]
PORT RXD3 = CONN_JX1_B15, IO_IS = ETH_RXD[3]
PORT COL = CONN_JX1_B24, IO_IS=ETH_COL
PORT RXER = CONN_JX1_B19, IO_IS=ETH_RXER
PORT TXEN = CONN_JX1_B21, IO_IS=ETH_TXEN
PORT TXD0 = CONN_JX1_A21, IO_IS = ETH_TXD[0]
PORT TXD1 = CONN_JX1_B22, IO_IS = ETH_TXD[1]
PORT TXD2 = CONN_JX1_B23, IO_IS = ETH_TXD[2]
PORT TXD3 = CONN_JX1_A23, IO_IS = ETH_TXD[3]
PORT MDC = CONN_JX1_B14, IO_IS=ETH_MDC
PORT RESETn = CONN_JX1_B31, IO_IS=PHY_RESETn
PORT MDIO = CONN_JX1_A13, IO_IS=ETH_MDIO
END

# Total 512 MB arranged as 64Mx64
# Uses Micron Tech MT8VDDT6464A 512MB unbufferd DIMM CL = 2.5 (512 MB dual rank)
# OR uses Kingston KVR266X64C25/512 512 MB 266 Mhz DDR PC2100 DIMM CL2.5 (512 MB dual rank)
BEGIN IO_INTERFACE
ATTRIBUTE IOTYPE = XIL_DDR_V1
ATTRIBUTE INSTANCE = DDR_512MB_64Mx64_rank2_row13_col10_cl2_5
ATTRIBUTE EXCLUSIVE = ddr_1rank_2rank
ATTRIBUTE ALERT = 'Micron Tech MT8VDDT6464A or Kingston KVR266X64C25/512 512MB unbufferd duak rank DIMM module minimum clock frequency of 75Mhz to operate properly.'
PARAMETER C_NUM_BANKS_MEM = 2, IO_IS=C_NUM_BANKS_MEM
PARAMETER C_MEM0_BASEADDR = 0x00000000, IO_IS=C_BASEADDR, SHORT_DESC=DDR_SDRAM_64Mx64 Dual Rank
PARAMETER C_MEM0_HIGHADDR = 0x0fffffff, IO_IS=C_HIGHADDR
PARAMETER C_MEM1_BASEADDR = 0x10000000, IO_IS=C_MEM1_BASEADDR
PARAMETER C_MEM1_HIGHADDR = 0x1fffffff, IO_IS=C_MEM1_HIGHADDR
PARAMETER C_NUM_CLK_PAIRS = 3, IO_IS=C_NUM_CLK_PAIRS
PARAMETER C_INCLUDE_BURST_CACHELN_SUPPORT = 1, IO_IS=C_INCLUDE_BURST_CACHELN_SUPPORT
PARAMETER C_REG_DIMM = 0, IO_IS=C_REG_DIMM
PARAMETER C_DDR_TMRD = 12000, IO_IS=C_DDR_TMRD
PARAMETER C_DDR_TWR = 15000, IO_IS=C_DDR_TWR
PARAMETER C_DDR_TRAS = 42000, IO_IS=C_DDR_TRAS
PARAMETER C_DDR_TRC = 60000, IO_IS=C_DDR_TRC
PARAMETER C_DDR_TRFC = 72000, IO_IS=C_DDR_TRFC
PARAMETER C_DDR_TRCD = 18000, IO_IS=C_DDR_TRCD
PARAMETER C_DDR_TRRD = 12000, IO_IS=C_DDR_TRRD
PARAMETER C_DDR_TRP = 18000, IO_IS=C_DDR_TRP
PARAMETER C_DDR_TREFC = 64000000, IO_IS=C_DDR_TREFC
PARAMETER C_DDR_AWIDTH = 13, IO_IS=C_DDR_AWIDTH
PARAMETER C_DDR_COL_AWIDTH = 11, IO_IS=C_DDR_COL_AWIDTH
PARAMETER C_DDR_BANK_AWIDTH = 2, IO_IS=C_DDR_BANK_AWIDTH
PARAMETER C_DDR_DWIDTH = 64, IO_IS=C_DDR_DWIDTH
# Support for 64bit opb_ddr controller starts in EDK 7.1.2

PORT A0 = ddr_1rank_2rank_addr_0_, IO_IS=address[12]
PORT A1 = ddr_1rank_2rank_addr_1_, IO_IS=address[11]
PORT A2 = ddr_1rank_2rank_addr_2_, IO_IS=address[10]
PORT A3 = ddr_1rank_2rank_addr_3_, IO_IS=address[9]
PORT A4 = ddr_1rank_2rank_addr_4_, IO_IS=address[8]
PORT A5 = ddr_1rank_2rank_addr_5_, IO_IS=address[7]
PORT A6 = ddr_1rank_2rank_addr_6_, IO_IS=address[6]
PORT A7 = ddr_1rank_2rank_addr_7_, IO_IS=address[5]
PORT A8 = ddr_1rank_2rank_addr_8_, IO_IS=address[4]
PORT A9 = ddr_1rank_2rank_addr_9_, IO_IS=address[3]
PORT A10 = ddr_1rank_2rank_addr_10_, IO_IS=address[2]
PORT A11 = ddr_1rank_2rank_addr_11_, IO_IS=address[1]
PORT A12 = ddr_1rank_2rank_addr_12_, IO_IS=address[0]
PORT BA0 = ddr_1rank_2rank_ba_0_, IO_IS=bank_addr[1]
PORT BA1 = ddr_1rank_2rank_ba_1_, IO_IS=bank_addr[0]
PORT CAS = ddr_1rank_2rank_cas_n, IO_IS=col_addr_select

PORT CKE0 = ddr_2rank_cke_0_, IO_IS=clk_enable[1]
PORT CKE1 = ddr_2rank_cke_1_, IO_IS=clk_enable[0]
PORT CS0 = ddr_2rank_cs_n_0_, IO_IS=chip_select[1]
PORT CS1 = ddr_2rank_cs_n_1_, IO_IS=chip_select[0]

PORT RAS = ddr_1rank_2rank_ras_n, IO_IS=row_addr_select
PORT WE = ddr_1rank_2rank_we_n, IO_IS=write_enable
PORT DM0 = ddr_1rank_2rank_dm_0_, IO_IS = data_mask[7]
PORT DM1 = ddr_1rank_2rank_dm_1_, IO_IS = data_mask[6]
PORT DM2 = ddr_1rank_2rank_dm_2_, IO_IS = data_mask[5]
PORT DM3 = ddr_1rank_2rank_dm_3_, IO_IS = data_mask[4]
PORT DM4 = ddr_1rank_2rank_dm_4_, IO_IS = data_mask[3]
PORT DM5 = ddr_1rank_2rank_dm_5_, IO_IS = data_mask[2]
PORT DM6 = ddr_1rank_2rank_dm_6_, IO_IS = data_mask[1]
PORT DM7 = ddr_1rank_2rank_dm_7_, IO_IS = data_mask[0]

PORT DQS0 = ddr_1rank_2rank_dqs_0_, IO_IS = data_strobe[7]
PORT DQS1 = ddr_1rank_2rank_dqs_1_, IO_IS = data_strobe[6]
PORT DQS2 = ddr_1rank_2rank_dqs_2_, IO_IS = data_strobe[5]
PORT DQS3 = ddr_1rank_2rank_dqs_3_, IO_IS = data_strobe[4]
PORT DQS4 = ddr_1rank_2rank_dqs_4_, IO_IS = data_strobe[3]
PORT DQS5 = ddr_1rank_2rank_dqs_5_, IO_IS = data_strobe[2]
PORT DQS6 = ddr_1rank_2rank_dqs_6_, IO_IS = data_strobe[1]
PORT DQS7 = ddr_1rank_2rank_dqs_7_, IO_IS = data_strobe[0]

PORT DQ0 = ddr_1rank_2rank_dq_0_, IO_IS = data[63]
PORT DQ1 = ddr_1rank_2rank_dq_1_, IO_IS = data[62]
PORT DQ2 = ddr_1rank_2rank_dq_2_, IO_IS = data[61]
PORT DQ3 = ddr_1rank_2rank_dq_3_, IO_IS = data[60]
PORT DQ4 = ddr_1rank_2rank_dq_4_, IO_IS = data[59]
PORT DQ5 = ddr_1rank_2rank_dq_5_, IO_IS = data[58]
PORT DQ6 = ddr_1rank_2rank_dq_6_, IO_IS = data[57]
PORT DQ7 = ddr_1rank_2rank_dq_7_, IO_IS = data[56]
PORT DQ8 = ddr_1rank_2rank_dq_8_, IO_IS = data[55]
PORT DQ9 = ddr_1rank_2rank_dq_9_, IO_IS = data[54]
PORT DQ10 = ddr_1rank_2rank_dq_10_, IO_IS = data[53]
PORT DQ11 = ddr_1rank_2rank_dq_11_, IO_IS = data[52]
PORT DQ12 = ddr_1rank_2rank_dq_12_, IO_IS = data[51]
PORT DQ13 = ddr_1rank_2rank_dq_13_, IO_IS = data[50]
PORT DQ14 = ddr_1rank_2rank_dq_14_, IO_IS = data[49]
PORT DQ15 = ddr_1rank_2rank_dq_15_, IO_IS = data[48]
PORT DQ16 = ddr_1rank_2rank_dq_16_, IO_IS = data[47]
PORT DQ17 = ddr_1rank_2rank_dq_17_, IO_IS = data[46]
PORT DQ18 = ddr_1rank_2rank_dq_18_, IO_IS = data[45]
PORT DQ19 = ddr_1rank_2rank_dq_19_, IO_IS = data[44]
PORT DQ20 = ddr_1rank_2rank_dq_20_, IO_IS = data[43]
PORT DQ21 = ddr_1rank_2rank_dq_21_, IO_IS = data[42]
PORT DQ22 = ddr_1rank_2rank_dq_22_, IO_IS = data[41]
PORT DQ23 = ddr_1rank_2rank_dq_23_, IO_IS = data[40]
PORT DQ24 = ddr_1rank_2rank_dq_24_, IO_IS = data[39]
PORT DQ25 = ddr_1rank_2rank_dq_25_, IO_IS = data[38]
PORT DQ26 = ddr_1rank_2rank_dq_26_, IO_IS = data[37]
PORT DQ27 = ddr_1rank_2rank_dq_27_, IO_IS = data[36]
PORT DQ28 = ddr_1rank_2rank_dq_28_, IO_IS = data[35]
PORT DQ29 = ddr_1rank_2rank_dq_29_, IO_IS = data[34]
PORT DQ30 = ddr_1rank_2rank_dq_30_, IO_IS = data[33]
PORT DQ31 = ddr_1rank_2rank_dq_31_, IO_IS = data[32]
PORT DQ32 = ddr_1rank_2rank_dq_32_, IO_IS = data[31]
PORT DQ33 = ddr_1rank_2rank_dq_33_, IO_IS = data[30]
PORT DQ34 = ddr_1rank_2rank_dq_34_, IO_IS = data[29]
PORT DQ35 = ddr_1rank_2rank_dq_35_, IO_IS = data[28]
PORT DQ36 = ddr_1rank_2rank_dq_36_, IO_IS = data[27]
PORT DQ37 = ddr_1rank_2rank_dq_37_, IO_IS = data[26]
PORT DQ38 = ddr_1rank_2rank_dq_38_, IO_IS = data[25]
PORT DQ39 = ddr_1rank_2rank_dq_39_, IO_IS = data[24]
PORT DQ40 = ddr_1rank_2rank_dq_40_, IO_IS = data[23]
PORT DQ41 = ddr_1rank_2rank_dq_41_, IO_IS = data[22]
PORT DQ42 = ddr_1rank_2rank_dq_42_, IO_IS = data[21]
PORT DQ43 = ddr_1rank_2rank_dq_43_, IO_IS = data[20]
PORT DQ44 = ddr_1rank_2rank_dq_44_, IO_IS = data[19]
PORT DQ45 = ddr_1rank_2rank_dq_45_, IO_IS = data[18]
PORT DQ46 = ddr_1rank_2rank_dq_46_, IO_IS = data[17]
PORT DQ47 = ddr_1rank_2rank_dq_47_, IO_IS = data[16]
PORT DQ48 = ddr_1rank_2rank_dq_48_, IO_IS = data[15]
PORT DQ49 = ddr_1rank_2rank_dq_49_, IO_IS = data[14]
PORT DQ50 = ddr_1rank_2rank_dq_50_, IO_IS = data[13]
PORT DQ51 = ddr_1rank_2rank_dq_51_, IO_IS = data[12]
PORT DQ52 = ddr_1rank_2rank_dq_52_, IO_IS = data[11]
PORT DQ53 = ddr_1rank_2rank_dq_53_, IO_IS = data[10]
PORT DQ54 = ddr_1rank_2rank_dq_54_, IO_IS = data[9]
PORT DQ55 = ddr_1rank_2rank_dq_55_, IO_IS = data[8]
PORT DQ56 = ddr_1rank_2rank_dq_56_, IO_IS = data[7]
PORT DQ57 = ddr_1rank_2rank_dq_57_, IO_IS = data[6]
PORT DQ58 = ddr_1rank_2rank_dq_58_, IO_IS = data[5]
PORT D5Q9 = ddr_1rank_2rank_dq_59_, IO_IS = data[4]
PORT DQ60 = ddr_1rank_2rank_dq_60_, IO_IS = data[3]
PORT DQ61 = ddr_1rank_2rank_dq_61_, IO_IS = data[2]
PORT DQ62 = ddr_1rank_2rank_dq_62_, IO_IS = data[1]
PORT DQ63 = ddr_1rank_2rank_dq_63_, IO_IS = data[0]

PORT DDR_FPGA_CK0 = ddr_1rank_2rank_clk_0_, IO_IS=DDR_Clk_out[2]
PORT DDR_FPGA_CK1 = ddr_1rank_2rank_clk_1_, IO_IS=DDR_Clk_out[1]
PORT DDR_FPGA_CK2 = ddr_1rank_2rank_clk_2_, IO_IS=DDR_Clk_out[0]
PORT DDR_FPGA_CK_N0 = ddr_1rank_2rank_clk_n_0_, IO_IS=DDR_Clk_out_n[2]
PORT DDR_FPGA_CK_N1 = ddr_1rank_2rank_clk_n_1_, IO_IS=DDR_Clk_out_n[1]
PORT DDR_FPGA_CK_N2 = ddr_1rank_2rank_clk_n_2_, IO_IS=DDR_Clk_out_n[0]

PORT DDR_FB_CLK = ddr_1rank_2rank_clk_fb, IO_IS=feedback_clock, FEEDBACK_PHASE=0
PORT DDR_FB_CLK_OUT = ddr_1rank_2rank_clk_fb_out, IO_IS=feedback_clock_out
END



BEGIN FPGA
ATTRIBUTE INSTANCE = fpga_0
ATTRIBUTE FAMILY = virtex2p
ATTRIBUTE DEVICE = xc2vp30
ATTRIBUTE PACKAGE = ff1152
ATTRIBUTE SPEED_GRADE = -7
ATTRIBUTE JTAG_POSITION = 2

PORT USER_SYS_CLK = CLK_100MHZ_OSC, UCF_NET_STRING=("LOC=H18", "IOSTANDARD = LVCMOS33") # Input CLK
### RESET ###
#PORT RESET = CONN_FPGA.RESET, UCF_NET_STRING=("LOC=P4", "IOSTANDARD = LVCMOS33", "PULLDOWN")
PORT RESET = CONN_FPGA.RESET, UCF_NET_STRING=("LOC=P4", "IOSTANDARD = LVCMOS33", "PULLDOWN")

### UART ###
#PORT RXD_DCE = CONN_RXD_DCE, UCF_NET_STRING=("LOC=AD26", "IOSTANDARD = LVCMOS25")
#PORT TXD_DCE = CONN_TXD_DCE, UCF_NET_STRING=("LOC=AG31", "IOSTANDARD = LVCMOS25")
#Without tritonmodule
PORT RXD_DCE = CONN_RXD_DCE, UCF_NET_STRING=("LOC=F4", "IOSTANDARD = LVCMOS33")
PORT TXD_DCE = CONN_TXD_DCE, UCF_NET_STRING=("LOC=J5", "IOSTANDARD = LVCMOS33")


### Ethernet ###
PORT ETH_TXER = CONN_JX1_A19, UCF_NET_STRING=("LOC=AL33", "IOSTANDARD = LVCMOS25")
PORT ETH_TXC = CONN_JX1_A35, UCF_NET_STRING=("LOC=AJ18", "IOSTANDARD = LVCMOS25")
PORT ETH_RXC = CONN_JX1_A33, UCF_NET_STRING=("LOC=AK17", "IOSTANDARD = LVCMOS25")
PORT ETH_CRS = CONN_JX1_B25, UCF_NET_STRING=("LOC=AH32", "IOSTANDARD = LVCMOS25")
PORT ETH_RXDV = CONN_JX1_A17, UCF_NET_STRING=("LOC=AJ34", "IOSTANDARD = LVCMOS25")
PORT ETH_RXD_0 = CONN_JX1_B17, UCF_NET_STRING=("LOC=AK34", "IOSTANDARD = LVCMOS25")
PORT ETH_RXD_1 = CONN_JX1_B16, UCF_NET_STRING=("LOC=AF27", "IOSTANDARD = LVCMOS25")
PORT ETH_RXD_2 = CONN_JX1_A15, UCF_NET_STRING=("LOC=AF28", "IOSTANDARD = LVCMOS25")
PORT ETH_RXD_3 = CONN_JX1_B15, UCF_NET_STRING=("LOC=AJ33", "IOSTANDARD = LVCMOS25")
PORT ETH_COL = CONN_JX1_B24, UCF_NET_STRING=("LOC=AD25", "IOSTANDARD = LVCMOS325")
PORT ETH_RXER = CONN_JX1_B19, UCF_NET_STRING=("LOC=AH31", "IOSTANDARD = LVCMOS25")
PORT ETH_TXEN = CONN_JX1_B21, UCF_NET_STRING=("LOC=AG28", "IOSTANDARD = LVCMOS25")
PORT ETH_TXD_0 = CONN_JX1_A21, UCF_NET_STRING=("LOC=AK31", "IOSTANDARD = LVCMOS25")
PORT ETH_TXD_1 = CONN_JX1_B22, UCF_NET_STRING=("LOC=AH29", "IOSTANDARD = LVCMOS25")
PORT ETH_TXD_2 = CONN_JX1_B23, UCF_NET_STRING=("LOC=AH30", "IOSTANDARD = LVCMOS25")
PORT ETH_TXD_3 = CONN_JX1_A23, UCF_NET_STRING=("LOC=AH27", "IOSTANDARD = LVCMOS25")
PORT ETH_MDC = CONN_JX1_B14, UCF_NET_STRING=("LOC=AG29", "IOSTANDARD = LVCMOS25")
PORT PHY_RESETn = CONN_JX1_B31, UCF_NET_STRING=("LOC=AK33", "IOSTANDARD = LVCMOS25")
PORT ETH_MDIO = CONN_JX1_A13, UCF_NET_STRING=("LOC=AL34", "IOSTANDARD = LVCMOS25")

# DDR SDRAM 64Mx64
PORT DDR_CLK2 = ddr_1rank_2rank_clk_2_, UCF_NET_STRING=("LOC=AE17", "IOSTANDARD = SSTL2_II")
PORT DDR_CLK1 = ddr_1rank_2rank_clk_1_, UCF_NET_STRING=("LOC=W29", "IOSTANDARD = SSTL2_II")
PORT DDR_CLK0 = ddr_1rank_2rank_clk_0_, UCF_NET_STRING=("LOC=AG17", "IOSTANDARD = SSTL2_II")
PORT DDR_CLKN2 = ddr_1rank_2rank_clk_n_2_, UCF_NET_STRING=("LOC=AD17", "IOSTANDARD = SSTL2_II")
PORT DDR_CLKN1 = ddr_1rank_2rank_clk_n_1_, UCF_NET_STRING=("LOC=W30", "IOSTANDARD = SSTL2_II")
PORT DDR_CLKN0 = ddr_1rank_2rank_clk_n_0_, UCF_NET_STRING=("LOC=AF17", "IOSTANDARD = SSTL2_II")
PORT DDR_A12 = ddr_1rank_2rank_addr_12_, UCF_NET_STRING=("LOC=AK16", "IOSTANDARD = SSTL2_II")
PORT DDR_A11 = ddr_1rank_2rank_addr_11_, UCF_NET_STRING=("LOC=AG22", "IOSTANDARD = SSTL2_II")
PORT DDR_A10 = ddr_1rank_2rank_addr_10_, UCF_NET_STRING=("LOC=AK21", "IOSTANDARD = SSTL2_II")
PORT DDR_A9 = ddr_1rank_2rank_addr_9_, UCF_NET_STRING=("LOC=AH19", "IOSTANDARD = SSTL2_II")
PORT DDR_A8 = ddr_1rank_2rank_addr_8_, UCF_NET_STRING=("LOC=AF22", "IOSTANDARD = SSTL2_II")
PORT DDR_A7 = ddr_1rank_2rank_addr_7_, UCF_NET_STRING=("LOC=AJ19", "IOSTANDARD = SSTL2_II")
PORT DDR_A6 = ddr_1rank_2rank_addr_6_, UCF_NET_STRING=("LOC=AE22", "IOSTANDARD = SSTL2_II")
PORT DDR_A5 = ddr_1rank_2rank_addr_5_, UCF_NET_STRING=("LOC=AK19", "IOSTANDARD = SSTL2_II")
PORT DDR_A4 = ddr_1rank_2rank_addr_4_, UCF_NET_STRING=("LOC=AK27", "IOSTANDARD = SSTL2_II")
PORT DDR_A3 = ddr_1rank_2rank_addr_3_, UCF_NET_STRING=("LOC=AL21", "IOSTANDARD = SSTL2_II")
PORT DDR_A2 = ddr_1rank_2rank_addr_2_, UCF_NET_STRING=("LOC=AE27", "IOSTANDARD = SSTL2_II")
PORT DDR_A1 = ddr_1rank_2rank_addr_1_, UCF_NET_STRING=("LOC=AL22", "IOSTANDARD = SSTL2_II")
PORT DDR_A0 = ddr_1rank_2rank_addr_0_, UCF_NET_STRING=("LOC=AE28", "IOSTANDARD = SSTL2_II")
PORT DDR_BA0 = ddr_1rank_2rank_ba_0_, UCF_NET_STRING=("LOC=AK22", "IOSTANDARD = SSTL2_II")
PORT DDR_BA1 = ddr_1rank_2rank_ba_1_, UCF_NET_STRING=("LOC=AF29", "IOSTANDARD = SSTL2_II")
PORT DDR_CAS_N = ddr_1rank_2rank_cas_n, UCF_NET_STRING=("LOC=AF31", "IOSTANDARD = SSTL2_II", "PULLUP")

PORT DDR_RAS_N = ddr_1rank_2rank_ras_n, UCF_NET_STRING=("LOC=AF30", "IOSTANDARD = SSTL2_II", "PULLUP")
PORT DDR_WE_N = ddr_1rank_2rank_we_n, UCF_NET_STRING=("LOC=AL23", "IOSTANDARD = SSTL2_II", "PULLUP")
PORT DDR_DQM0 = ddr_1rank_2rank_dm_0_, UCF_NET_STRING=("LOC=AJ13", "IOSTANDARD = SSTL2_II")
PORT DDR_DQM1 = ddr_1rank_2rank_dm_1_, UCF_NET_STRING=("LOC=AG14", "IOSTANDARD = SSTL2_II")
PORT DDR_DQM2 = ddr_1rank_2rank_dm_2_, UCF_NET_STRING=("LOC=AF21", "IOSTANDARD = SSTL2_II")
PORT DDR_DQM3 = ddr_1rank_2rank_dm_3_, UCF_NET_STRING=("LOC=AM13", "IOSTANDARD = SSTL2_II")
PORT DDR_DQM4 = ddr_1rank_2rank_dm_4_, UCF_NET_STRING=("LOC=AG33", "IOSTANDARD = SSTL2_II")
PORT DDR_DQM5 = ddr_1rank_2rank_dm_5_, UCF_NET_STRING=("LOC=AC25", "IOSTANDARD = SSTL2_II")
PORT DDR_DQM6 = ddr_1rank_2rank_dm_6_, UCF_NET_STRING=("LOC=W27", "IOSTANDARD = SSTL2_II")
PORT DDR_DQM7 = ddr_1rank_2rank_dm_7_, UCF_NET_STRING=("LOC=V28", "IOSTANDARD = SSTL2_II")
PORT DDR_DQS0 = ddr_1rank_2rank_dqs_0_, UCF_NET_STRING=("LOC=AG10", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQS1 = ddr_1rank_2rank_dqs_1_, UCF_NET_STRING=("LOC=AK14", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQS2 = ddr_1rank_2rank_dqs_2_, UCF_NET_STRING=("LOC=AH10", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQS3 = ddr_1rank_2rank_dqs_3_, UCF_NET_STRING=("LOC=AE18", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQS4 = ddr_1rank_2rank_dqs_4_, UCF_NET_STRING=("LOC=AF25", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQS5 = ddr_1rank_2rank_dqs_5_, UCF_NET_STRING=("LOC=AC29", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQS6 = ddr_1rank_2rank_dqs_6_, UCF_NET_STRING=("LOC=AC34", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQS7 = ddr_1rank_2rank_dqs_7_, UCF_NET_STRING=("LOC=AC28", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ63 = ddr_1rank_2rank_dq_63_, UCF_NET_STRING=("LOC=V26", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ62 = ddr_1rank_2rank_dq_62_, UCF_NET_STRING=("LOC=V27", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ61 = ddr_1rank_2rank_dq_61_, UCF_NET_STRING=("LOC=V29", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ60 = ddr_1rank_2rank_dq_60_, UCF_NET_STRING=("LOC=V30", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ59 = ddr_1rank_2rank_dq_59_, UCF_NET_STRING=("LOC=AC26", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ58 = ddr_1rank_2rank_dq_58_, UCF_NET_STRING=("LOC=Y28", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ57 = ddr_1rank_2rank_dq_57_, UCF_NET_STRING=("LOC=Y29", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ56 = ddr_1rank_2rank_dq_56_, UCF_NET_STRING=("LOC=Y31", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ55 = ddr_1rank_2rank_dq_55_, UCF_NET_STRING=("LOC=V31", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ54 = ddr_1rank_2rank_dq_54_, UCF_NET_STRING=("LOC=V32", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ53 = ddr_1rank_2rank_dq_53_, UCF_NET_STRING=("LOC=W28", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ52 = ddr_1rank_2rank_dq_52_, UCF_NET_STRING=("LOC=W31", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ51 = ddr_1rank_2rank_dq_51_, UCF_NET_STRING=("LOC=Y33", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ50 = ddr_1rank_2rank_dq_50_, UCF_NET_STRING=("LOC=AA33", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ49 = ddr_1rank_2rank_dq_49_, UCF_NET_STRING=("LOC=AB33", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ48 = ddr_1rank_2rank_dq_48_, UCF_NET_STRING=("LOC=AD29", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ47 = ddr_1rank_2rank_dq_47_, UCF_NET_STRING=("LOC=W32", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ46 = ddr_1rank_2rank_dq_46_, UCF_NET_STRING=("LOC=AD19", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ45 = ddr_1rank_2rank_dq_45_, UCF_NET_STRING=("LOC=AD28", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ44 = ddr_1rank_2rank_dq_44_, UCF_NET_STRING=("LOC=AD27", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ43 = ddr_1rank_2rank_dq_43_, UCF_NET_STRING=("LOC=AD30", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ42 = ddr_1rank_2rank_dq_42_, UCF_NET_STRING=("LOC=AD31", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ41 = ddr_1rank_2rank_dq_41_, UCF_NET_STRING=("LOC=AE31", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ40 = ddr_1rank_2rank_dq_40_, UCF_NET_STRING=("LOC=AE24", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ39 = ddr_1rank_2rank_dq_39_, UCF_NET_STRING=("LOC=AE33", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ38 = ddr_1rank_2rank_dq_38_, UCF_NET_STRING=("LOC=AF33", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ37 = ddr_1rank_2rank_dq_37_, UCF_NET_STRING=("LOC=AH33", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ36 = ddr_1rank_2rank_dq_36_, UCF_NET_STRING=("LOC=AH34", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ35 = ddr_1rank_2rank_dq_35_, UCF_NET_STRING=("LOC=AG25", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ34 = ddr_1rank_2rank_dq_34_, UCF_NET_STRING=("LOC=AH25", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ33 = ddr_1rank_2rank_dq_33_, UCF_NET_STRING=("LOC=AJ24", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ32 = ddr_1rank_2rank_dq_32_, UCF_NET_STRING=("LOC=AK24", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ31 = ddr_1rank_2rank_dq_31_, UCF_NET_STRING=("LOC=AF18", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ30 = ddr_1rank_2rank_dq_30_, UCF_NET_STRING=("LOC=AJ16", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ29 = ddr_1rank_2rank_dq_29_, UCF_NET_STRING=("LOC=AH14", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ28 = ddr_1rank_2rank_dq_28_, UCF_NET_STRING=("LOC=AH15", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ27 = ddr_1rank_2rank_dq_27_, UCF_NET_STRING=("LOC=AF13", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ26 = ddr_1rank_2rank_dq_26_, UCF_NET_STRING=("LOC=AF15", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ25 = ddr_1rank_2rank_dq_25_, UCF_NET_STRING=("LOC=AD16", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ24 = ddr_1rank_2rank_dq_24_, UCF_NET_STRING=("LOC=AE19", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ23 = ddr_1rank_2rank_dq_23_, UCF_NET_STRING=("LOC=AM21", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ22 = ddr_1rank_2rank_dq_22_, UCF_NET_STRING=("LOC=AM22", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ21 = ddr_1rank_2rank_dq_21_, UCF_NET_STRING=("LOC=AG21", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ20 = ddr_1rank_2rank_dq_20_, UCF_NET_STRING=("LOC=AF20", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ19 = ddr_1rank_2rank_dq_19_, UCF_NET_STRING=("LOC=AE20", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ18 = ddr_1rank_2rank_dq_18_, UCF_NET_STRING=("LOC=AE21", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ17 = ddr_1rank_2rank_dq_17_, UCF_NET_STRING=("LOC=AF14", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ16 = ddr_1rank_2rank_dq_16_, UCF_NET_STRING=("LOC=AH13", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ15 = ddr_1rank_2rank_dq_15_, UCF_NET_STRING=("LOC=AG19", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ14 = ddr_1rank_2rank_dq_14_, UCF_NET_STRING=("LOC=AF19", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ13 = ddr_1rank_2rank_dq_13_, UCF_NET_STRING=("LOC=AF16", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ12 = ddr_1rank_2rank_dq_12_, UCF_NET_STRING=("LOC=AG16", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ11 = ddr_1rank_2rank_dq_11_, UCF_NET_STRING=("LOC=AL14", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ10 = ddr_1rank_2rank_dq_10_, UCF_NET_STRING=("LOC=AM14", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ9 = ddr_1rank_2rank_dq_9_, UCF_NET_STRING=("LOC=AK13", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ8 = ddr_1rank_2rank_dq_8_, UCF_NET_STRING=("LOC=AK11", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ7 = ddr_1rank_2rank_dq_7_, UCF_NET_STRING=("LOC=AJ15", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ6 = ddr_1rank_2rank_dq_6_, UCF_NET_STRING=("LOC=AJ14", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ5 = ddr_1rank_2rank_dq_5_, UCF_NET_STRING=("LOC=AL13", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ4 = ddr_1rank_2rank_dq_4_, UCF_NET_STRING=("LOC=AL12", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ3 = ddr_1rank_2rank_dq_3_, UCF_NET_STRING=("LOC=AL11", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ2 = ddr_1rank_2rank_dq_2_, UCF_NET_STRING=("LOC=AJ11", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ1 = ddr_1rank_2rank_dq_1_, UCF_NET_STRING=("LOC=AG13", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")
PORT DDR_DQ0 = ddr_1rank_2rank_dq_0_, UCF_NET_STRING=("LOC=AK8", "IOSTANDARD = SSTL2_II_DCI")
PORT DDR_CLK_FB = ddr_1rank_2rank_clk_fb, UCF_NET_STRING=("LOC=AH17", "IOSTANDARD = SSTL2_II")
PORT DDR_CLK_FB_OUT = ddr_1rank_2rank_clk_fb_out, UCF_NET_STRING=("LOC=Y34", "IOSTANDARD = SSTL2_II")

PORT DDR_CKE0 = ddr_2rank_cke_0_, UCF_NET_STRING=("LOC=AJ22", "IOSTANDARD = SSTL2_II")
PORT DDR_CKE1 = ddr_2rank_cke_1_, UCF_NET_STRING=("LOC=AE11", "IOSTANDARD = SSTL2_II")
PORT DDR_CS_N0 = ddr_2rank_cs_n_0_, UCF_NET_STRING=("LOC=AL24", "IOSTANDARD = SSTL2_II")
PORT DDR_CS_N1 = ddr_2rank_cs_n_1_, UCF_NET_STRING=("LOC=Af32", "IOSTANDARD = SSTL2_II")



END

============================================

NET "fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_RASn_pin" PULLUP;
NET "fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CASn_pin" PULLUP;
NET "fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_WEn_pin"; PULLUP;
#NET "SODIMM_S*"; PULLUP;
NET "fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin<*>" PULLDOWN;
NET "fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin<*&gt;" PULLDOWN;


NET "fpga_0_DDR_CLK_FB" TNM_NET = "fpga_0_DDR_CLK_FB";
TIMESPEC "TS_fpga_0_DDR_CLK_FB&quot; = PERIOD "fpga_0_DDR_CLK_FB" 92.16 MHz HIGH 50 %;

INST "dcm_0/dcm_0/DCM_INST&quot; LOC = "DCM_X3Y0";

# DDR_Clk_270
inst "dcm_1/dcm_1/DCM_INST&quot; loc = "DCM_X0Y0";

# Feedback
inst "dcm_2/dcm_2/DCM_INST&quot; loc = "DCM_X1Y0";
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5 Replies
Xilinx Employee
Xilinx Employee
12,482 Views
Registered: ‎08-15-2007

Re: DDR on custom board with EDK 8.1.02i

Have you tried locking down the BUFGs also?
The ethernet core will add additional BUFGs so this could be moving the BUFGs around which could be causing slight timing variations. 
What is the minimum frequency of your DDR memory, is 92.16 MHz within spec?
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Adventurer
Adventurer
12,456 Views
Registered: ‎08-16-2007

Re: DDR on custom board with EDK 8.1.02i

Check Answer Record: 23812
http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=23812
Do this for both rx_clk and tx_clk of your ethernet_lite core
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Visitor durano
Visitor
12,448 Views
Registered: ‎09-17-2007

Re: DDR on custom board with EDK 8.1.02i

Thanks for your answers!
 
I tested locking the BUFG's and it seems to do the trick.
(Cant realize I haven't thought of it on my own)
 
Many thanks
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Newbie davemeen
Newbie
12,377 Views
Registered: ‎09-28-2007

Re: DDR on custom board with EDK 8.1.02i

I am also having trouble getting a DDR SDRAM working with a VIrtex-4 FX12 on my custom board.
I am using DCI instead of using termination resistors for the DDR SDRAM-to-FX12 interface.

Are you also using DCI instead of termination resistors, or possibly a mixture of both?


I was wondering if you could post your .ucf file so that I can see the settings for the fpga pins that connect to the DDR SDRAM.
This is because in your posting, I could not understand what the "&quot" meant.
For example,

PORT DDR_DQM2 = ddr_1rank_2rank_dm_2_, UCF_NET_STRING=(&quot;LOC=AF21", "IOSTANDARD = SSTL2_II&quot;)

I was also wondering why PULLDOWN and PULLUP were used when setting the IOSTANDARD.
Possibly this is related only to your custom board, but maybe it is something I should also be doing.
For example,

PORT DDR_DQS1 = ddr_1rank_2rank_dqs_1_, UCF_NET_STRING=(&quot;LOC=AK14", "IOSTANDARD = SSTL2_II_DCI", "PULLDOWN")

I thought possibly the setting for bidirectional signals like DQS and DQ should use SSTL2_II_DCI, which is SSTL2, Class II.
I think you have them set for this.
But for one-directional signals I thought that SSTL2_I_DCI should be used instead. This is SSTL2, Class I.
I think it will save a lot of current.

Have you had any heat problems with the FX12 since you are using DCI?


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Visitor durano
Visitor
12,368 Views
Registered: ‎09-17-2007

Re: DDR on custom board with EDK 8.1.02i

Sorry I cant really answer if the board has resistors atm. As I'm not able to access the board or its schematics this weekend. And my memory fails me : /
 
But your question about "&quot" its not really a part of the file. This forum script made thoose so what should stand instead is a " sign:
 
&quot = "
 
The pulldown or pullup are most likely because of the board making, dont remember.
 
About the DCI if I remember correctly the routing on the board are different for the DQS and DQ signals and becouse of that the IO standard used are DCI, this should be related to the bi bidirectional od the signals.
 
I've only used the Virtex II pro myself, but with this I haven't had any heat problems. But the Virtex4 are a bit different I guess.
 
Sorry I cant be much of a help at the moment.
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