05-12-2009 08:15 AM
I have a XpressGen2V5-FXT70 board from PLDA with a DDR2 chip MT47H64M16HR-3:G.
I've implemented a MPMC with only a PLB 64 bits port, but the problem is that the controler never rises the init_done signal, like the MPMC was not alive as nothing happends !
Here is a piece of my MHS :
PARAMETER INSTANCE = OpbSdram
PARAMETER HW_VER = 4.03.a
PARAMETER C_MEM_PARTNO = MT47H64M16-3
PARAMETER C_MPMC_CLK0_PERIOD_PS = 5000
PARAMETER C_MEM_DQS_IO_COL = 0b000000000000000000000000000000000000000000000000000000000000000000001010
PARAMETER C_MEM_DQ_IO_MS = 0b000000000000000000000000000000000000000000000000000000001101101100100110
PARAMETER C_MEM_DATA_WIDTH = 16
PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X2Y2
PARAMETER C_MPMC_BASEADDR = 0x00000000
PARAMETER C_MPMC_HIGHADDR = 0x07FFFFFF
PARAMETER C_MEM_ODT_TYPE = 3
PARAMETER C_MEM_REDUCED_DRV = 1
BUS_INTERFACE SPLB0 = PlbBus
PORT DDR2_DQS_n = DDR2_DQS_N
PORT DDR2_Addr = DDR2_A
PORT DDR2_BankAddr = DDR2_BA
PORT DDR2_WE_n = DDR2_WE_N
PORT DDR2_CAS_n = DDR2_CAS_N
PORT DDR2_RAS_n = DDR2_RAS_N
PORT DDR2_CS_n = DDR2_CS_N
PORT DDR2_Clk_n = DDR2_CK_N
PORT DDR2_Clk = DDR2_CK
PORT DDR2_DM = DDR2_DM
PORT DDR2_ODT = DDR2_ODT
PORT DDR2_DQS = DDR2_DQS
PORT DDR2_DQ = DDR2_DQ
PORT MPMC_Rst = sys_bus_reset
PORT MPMC_Clk_200MHz = clk_200_ddr2
PORT MPMC_Clk90 = clk_200_ddr2_90
PORT MPMC_Clk0_DIV2 = clk_100
PORT MPMC_Clk0 = clk_200_ddr2
PORT DDR2_CE = OpbSdram_DDR2_CE
Timings are Ok in ISE on all the DDR2 constraints that I had to change manually because IO are on banks 18/22/21/17, but a MIG 2.3 UCF check says they are OK.
Clocks are generated by the folowing PLL module :
PARAMETER INSTANCE = pll_module_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLKIN1_PERIOD = 20.000000
PARAMETER C_CLKOUT1_DESKEW_ADJUST = PPC
PARAMETER C_CLKFBOUT_BUF = true
PARAMETER C_CLKOUT0_BUF = true
PARAMETER C_CLKOUT1_BUF = true
PARAMETER C_CLKOUT2_BUF = true
PARAMETER C_CLKOUT2_PHASE = 90.000000
PARAMETER C_CLKOUT0_DIVIDE = 4
PARAMETER C_CLKOUT1_DIVIDE = 4
PARAMETER C_CLKOUT2_DIVIDE = 4
PARAMETER C_CLKOUT3_DIVIDE = 8
PARAMETER C_CLKOUT3_BUF = true
PARAMETER C_CLKFBOUT_MULT = 16
PORT RST = SystemReset_in
PORT LOCKED = pll_locked
PORT CLKOUT1 = clk_200_ddr2
PORT CLKOUT0 = clk_200_ppc
PORT CLKOUT2 = clk_200_ddr2_90
PORT CLKOUT3 = clk_100
PORT CLKFBIN = pll_fb
PORT CLKFBOUT = pll_fb
PORT CLKIN1 = clk_50_in
PLB is 100Mhz from this PLL.
One other thing, at the end of the ucf there is a list of constraints on u_ff_stg2a_rise that are not achieved beacause I have another IP which uses these slices, but ISE placed these constraints on the right of the IO instead of the left, but at the same slice so I guess timings are not much different anyway.
Where can I be wrong ?
05-13-2009 02:25 AM
I've just found that the CKE is forced to global_logic_0 !!!
So clock is never active on the chip !!
Why does ISE forces it to 0 ????!!!!
A bad configuration in the MPMC controller ?
05-13-2009 02:31 AM
I forced it to 1 but that doesn't work either !!
I guess start up / reset / init sequences are not correctly done because of the fixed CKE.
But I can't see why ISE forces it to 0 !!
05-13-2009 02:45 AM - edited 05-13-2009 03:02 AM
Got the answer !
I messed up in the EDK's external port declaration, as the MPMC peripheral has no CKE signal but a CE signal, so my CKE output was connected to nothing !!
But it still doesn't work......
05-13-2009 04:49 AM - edited 05-13-2009 05:01 AM
In fact the MPMC_InitDone signal is high on FPGA configuration but it goes low on first MPMC_Rst activation when I launch the GDB.
All others MPMC_Rst activation doesn't bring it back to 1.
05-13-2009 07:25 AM
In fact it seems that the PPC run the firmware correctly using the DDR2 until there is a reset, then the MPMC does not answer anymore.
I've made the reset larger using the sys_periph_reset instead of the sys_bus_reset but the result is the same.
Does anyone knows why the MPMC goes dead on resets ?
06-15-2009 06:15 AM
Don't know if it is at all related, but I am also having problems with MPMC function.
I had a working design, made a few minor changes to unrelated logic, rebuilt it, and
now the MPMC DDR2 interface completely fails to work. I am trying to track down
what it is about the build or constraints or whatever that results in a dead DDR2
interface. The location of much of the DDR2 interface is constrained so
timing shouldn't change, yet it goes from fully functional to completely dead for no
11-09-2009 10:34 AM
I am having same kind of problems with MB.
The MPMC seems totally dead, none of the signals coming from it toggels.
Did you got this problem solved, if yes how?
11-10-2009 01:44 AM
In my case the DDR2 apparently not functioning was a complete red herring.
The DDR2 was functioning but something else in the design was not working.
I tracked it down to a section of verilog I inherited from someone else's design
but never looked at very closely as it seemed to work. When I did look at it I
could see that it should never have worked, but rather surprisingly on some
synthesis runs it did work and on others it didn't resulting in some very
confusing symptoms. Does your MPMC work sometimes and not others ?
Are you using verilog ? I find verilog has very poor error checking and mistakes
that would never get through using VHDL are not picked up by the xilinx
synthesis tool. Whenever possible I run the code through modelsim to
check it before putting it through synthesis.
11-10-2009 02:25 AM
I am using VHDL.
MPMC doesn't work at all, it doesn't give any signals expect clock to out.
So it's quite a problem that this InitDone signal doesn't go high, this makes the desgin to be "silent", I think...
I haven't check the EDK designs with simulator, if only IPs are used.
01-20-2010 07:44 AM
I have confirmed that, in my design, the InitDone signal from mpmc never goes high - even after reset. I see that this problem has been encountered by some of those on this thread. Has anyone managed to solve it?
01-20-2010 07:51 AM
InitDone signal from MPMC not going high clearly suggests that something is not meeting the requirement inside. It will only go high when MPMC reads back successfully what it writes during PHY calibration of your DDR.
Check the things at your end once again. Also check the reset polarity as well of your system.
01-20-2010 08:14 AM
Thanks for the response! I'm relatively new here so I have a few follow-up questions:
First, could you please specify what the inside requirements are that you are referring to? Second, in checking the reset polarity, could you please tell me what the reset polarity should be?
01-21-2010 01:58 AM
There are many parameters for DDR2 controller. Check the timing parameters, check the UCF pin assignment, Check the MIG generated constraints.
Reset polarity is known to you beforehand. If its active high on your board then assign active high in EDK else active low.