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Observer enterliu2000
Observer
10,674 Views
Registered: ‎09-23-2009

DDR2 ucf

Now i meet some questions when i create a project using ML505,i only add the device of DDR2 and uart1.When i generate bitstream,i :meet the questions as below:

WARNING:NgdBuild:486 - Attribute "SIM_MODE" is not allowed on symbol
   "microblaze_0/Performance.Data_Flow_I/MUL_Unit_I/Use_HW_MUL.Using_DSP48_Archi
   tectures.No_MUL64.dsp_module_I3/Using_Virtex5.DSP48E_I1" of type "DSP48E".
   This attribute will be ignored.
WARNING:NgdBuild:486 - Attribute "SIM_MODE" is not allowed on symbol
   "microblaze_0/Performance.Data_Flow_I/MUL_Unit_I/Use_HW_MUL.Using_DSP48_Archi
   tectures.No_MUL64.dsp_module_I2/Using_Virtex5.DSP48E_I1" of type "DSP48E".
   This attribute will be ignored.
WARNING:NgdBuild:486 - Attribute "SIM_MODE" is not allowed on symbol
   "microblaze_0/Performance.Data_Flow_I/MUL_Unit_I/Use_HW_MUL.Using_DSP48_Archi
   tectures.dsp_module_I1/Using_Virtex5.DSP48E_I1" of type "DSP48E".  This
   attribute will be ignored.
WARNING:NgdBuild:443 - SFF primitive
   'DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/u
   _phy_calib_0/gen_rden[1].u_calib_rden_r' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/u
   _phy_calib_0/gen_rden[2].u_calib_rden_r' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/u
   _phy_calib_0/gen_rden[3].u_calib_rden_r' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/u
   _phy_calib_0/gen_rden[4].u_calib_rden_r' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/u
   _phy_calib_0/gen_rden[5].u_calib_rden_r' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/u
   _phy_calib_0/gen_rden[6].u_calib_rden_r' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/u
   _phy_calib_0/gen_rden[7].u_calib_rden_r' has unconnected output pin
WARNING:NgdBuild:452 - logical net 'N100' has no driver
WARNING:NgdBuild:452 - logical net 'N101' has no driver
WARNING:NgdBuild:452 - logical net 'N102' has no driver
WARNING:NgdBuild:452 - logical net 'N103' has no driver
WARNING:NgdBuild:452 - logical net 'N104' has no driver
WARNING:NgdBuild:452 - logical net 'N105' has no driver
WARNING:NgdBuild:452 - logical net 'N106' has no driver
WARNING:NgdBuild:452 - logical net 'N107' has no driver
WARNING:NgdBuild:452 - logical net 'N108' has no driver
WARNING:NgdBuild:452 - logical net 'N109' has no driver
WARNING:NgdBuild:452 - logical net 'N110' has no driver
WARNING:NgdBuild:452 - logical net 'N111' has no driver
WARNING:NgdBuild:452 - logical net 'N112' has no driver
WARNING:NgdBuild:452 - logical net 'N113' has no driver
WARNING:NgdBuild:452 - logical net 'N114' has no driver
WARNING:NgdBuild:452 - logical net 'N115' has no driver
WARNING:NgdBuild:452 - logical net 'N116' has no driver
WARNING:NgdBuild:452 - logical net 'N117' has no driver
WARNING:NgdBuild:452 - logical net 'N118' has no driver
WARNING:NgdBuild:452 - logical net 'N119' has no driver
WARNING:NgdBuild:452 - logical net 'N120' has no driver
WARNING:NgdBuild:452 - logical net 'N121' has no driver
WARNING:NgdBuild:452 - logical net 'N122' has no driver
WARNING:NgdBuild:452 - logical net 'N123' has no driver
WARNING:NgdBuild:452 - logical net 'N124' has no driver
WARNING:NgdBuild:452 - logical net 'N125' has no driver
WARNING:NgdBuild:452 - logical net 'N126' has no driver
WARNING:NgdBuild:452 - logical net 'N127' has no driver
WARNING:NgdBuild:452 - logical net 'N128' has no driver
WARNING:NgdBuild:452 - logical net 'N129' has no driver
WARNING:NgdBuild:452 - logical net 'N130' has no driver
WARNING:NgdBuild:452 - logical net 'N131' has no driver
WARNING:NgdBuild:452 - logical net 'N132' has no driver
WARNING:NgdBuild:452 - logical net 'N133' has no driver
WARNING:NgdBuild:452 - logical net 'N134' has no driver
WARNING:NgdBuild:452 - logical net 'N135' has no driver
WARNING:NgdBuild:452 - logical net 'N136' has no driver
WARNING:NgdBuild:452 - logical net 'N137' has no driver
WARNING:NgdBuild:452 - logical net 'N138' has no driver
WARNING:NgdBuild:452 - logical net 'N139' has no driver
WARNING:NgdBuild:452 - logical net 'N140' has no driver
WARNING:NgdBuild:452 - logical net 'N141' has no driver
WARNING:NgdBuild:452 - logical net 'N142' has no driver
WARNING:NgdBuild:452 - logical net 'N143' has no driver
WARNING:NgdBuild:452 - logical net 'N144' has no driver
WARNING:NgdBuild:452 - logical net 'N145' has no driver
WARNING:NgdBuild:452 - logical net 'N146' has no driver
WARNING:NgdBuild:452 - logical net 'N147' has no driver
WARNING:NgdBuild:452 - logical net 'N148' has no driver
WARNING:NgdBuild:452 - logical net 'N149' has no driver
WARNING:NgdBuild:452 - logical net 'N150' has no driver
WARNING:NgdBuild:452 - logical net 'N151' has no driver
WARNING:NgdBuild:452 - logical net 'N152' has no driver
WARNING:NgdBuild:452 - logical net 'N153' has no driver
WARNING:NgdBuild:452 - logical net 'N154' has no driver
WARNING:NgdBuild:452 - logical net 'N155' has no driver
WARNING:NgdBuild:452 - logical net 'N156' has no driver
WARNING:NgdBuild:452 - logical net 'N157' has no driver
WARNING:NgdBuild:452 - logical net 'N158' has no driver
WARNING:NgdBuild:452 - logical net 'N159' has no driver
WARNING:NgdBuild:452 - logical net 'N160' has no driver
WARNING:NgdBuild:452 - logical net 'N161' has no driver
WARNING:NgdBuild:452 - logical net 'N82' has no driver
WARNING:NgdBuild:452 - logical net 'N83' has no driver
WARNING:NgdBuild:452 - logical net 'N84' has no driver
WARNING:NgdBuild:452 - logical net 'N85' has no driver
WARNING:NgdBuild:452 - logical net 'N86' has no driver
WARNING:NgdBuild:452 - logical net 'N87' has no driver
WARNING:NgdBuild:452 - logical net 'N88' has no driver
WARNING:NgdBuild:452 - logical net 'N89' has no driver
WARNING:NgdBuild:452 - logical net 'N90' has no driver
WARNING:NgdBuild:452 - logical net 'N91' has no driver
WARNING:NgdBuild:452 - logical net 'N92' has no driver
WARNING:NgdBuild:452 - logical net 'N93' has no driver
WARNING:NgdBuild:452 - logical net 'N94' has no driver
WARNING:NgdBuild:452 - logical net 'N95' has no driver
WARNING:NgdBuild:452 - logical net 'N96' has no driver
WARNING:NgdBuild:452 - logical net 'N97' has no driver
WARNING:NgdBuild:452 - logical net 'N98' has no driver
WARNING:NgdBuild:452 - logical net 'N99' has no driver
WARNING:NgdBuild:478 - clock net debug_module/bscan_drck1 with clock driver
   debug_module/debug_module/BUFG_DRCK1 drives no clock pins

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  91

 

what cause these warnings,how can i resolve it?thank you!

PS:i have another question,that is,how can i get the position of DDR2 constraints,such as,

INST "*/gen_dq[63].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y119;

X0Y119,how can i get this value,thank you!

Tags (3)
0 Kudos
10 Replies
10,668 Views
Registered: ‎08-21-2008

Re: DDR2 ucf

Hello.

Those warnings are not critical warnings and they can be ignored.

As for your 2nd question what you can do is you bring your whole design in XPS to ISE and then you open FPGA editor and there you can see all the placements.

You will find FPGA editor under Place and Route in implementation in ISE. 

Best of luck.
--
Unlimited in my Limits.
0 Kudos
Observer enterliu2000
Observer
10,649 Views
Registered: ‎09-23-2009

Re: DDR2 ucf

Thank you for your answer.

i have tried to add the EDK project to the ISE,and i get a problem.That is,if some errors in the project ucf,the ISE can't pass the step of map.How can i solve it?

the error in my ucf is as below:

ERROR:Place:906 - Components driven by IO clock net
   <DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/d
   elayed_dqs<0>> can't be placed and routed because location constraints are
   causing the clock region rules to be violated. IO Clock net
   <DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/d
   elayed_dqs<0>> is being driven by BUFIO
   <DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/g
   en_dqs[0].u_iob_dqs/u_bufio_dqs> locked to site "BUFIO_X0Y16" Because of this
   location contraint,
   <DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/d
   elayed_dqs<0>> can only drive clock region "CLOCKREGION_X0Y4". The following
   components driven by
   <DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/d
   elayed_dqs<0>> have been locked to sites outside of these clock regions:
   DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/dq
   _ce<0> (Locked Site: ILOGIC_X0Y56 CLOCKREGION_X0Y1)
   DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/dq
   _ce<0> (Locked Site: ILOGIC_X0Y56 CLOCKREGION_X0Y1)
   Please evaluate the location constraints of both the BUFIO and the components
   driven by
   <DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/d
   elayed_dqs<0>> to ensure that they follow the clock region rules of the
   architecture. For more information on the clock region rules, please refer to
   the architecture user's guide. To debug your design with partially routed
   design, please allow mapper/placer to finish the execution (by setting
   environment variable XIL_PAR_DEBUG_IOCLKPLACER to 1).

 

i use four DQS in my design.if i don't pass this step,i can't use the FPGA editor to get the information.

Hope for your help!

0 Kudos
Observer enterliu2000
Observer
10,651 Views
Registered: ‎09-23-2009

Re: DDR2 ucf

hello,

   i have the other question,that is,how to set the value of DQS_IO_COL,i only know it is related with the position of DQS,how can i determine which is left,middle or right,so that we get the value of 00,01and 10,thank you!

0 Kudos
Xilinx Employee
Xilinx Employee
10,631 Views
Registered: ‎10-23-2007

Re: DDR2 ucf

Information on the DQS_IO_COL can be found on 45 of http://www.xilinx.com/support/documentation/application_notes/xapp858.pdf.  You may also find that AR 29313

is useful.

 

Are your DQS and associated DQ lines in the same bank?  If not, that could be why the tools are complaining about the BUFIO span.

 

0 Kudos
Observer enterliu2000
Observer
10,542 Views
Registered: ‎09-23-2009

Re: DDR2 ucf

Hi,

   now i met the problem as below,how can i resolve it,thank you! 

ERROR:Place:901 - IO Clock Net
   "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/d
   elayed_dqs<2>" cannot possibly be routed to component
   "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/d
   q_ce<2>" (placed in clock region "CLOCKREGION_X0Y5"), since it is too far
   away from source BUFIO
   "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/g
   en_dqs[2].u_iob_dqs/u_bufio_dqs" (placed in clock region "CLOCKREGION_X0Y4").
   The situation may be caused by user constraints, or the complexity of the
   design. Constraining the components related to the regional clock properly
   may guide the tool to find a solution.
   To debug your design with partially routed design, please try to allow
   map/placer to finish the execution (by setting environment variable
   XIL_PAR_DEBUG_IOCLKPLACER to 1).

 

 

0 Kudos
10,528 Views
Registered: ‎08-21-2008

Re: DDR2 ucf

Hello.

You get errors when you don't follow the MIG generated UCF assignment.

Is your UCF in accordance with the MIG. See if MIG passes your UCF.

Also try to set the environment variable as told in the Error and restart your PC and then again try to compile. 

Best of luck.
--
Unlimited in my Limits.
0 Kudos
Observer enterliu2000
Observer
10,474 Views
Registered: ‎09-23-2009

Re: DDR2 ucf

hi,

   Now i met a problem as below.i'd like to ask how can i solve it,thank you. 

 

   ERROR:MapLib:30 - LOC constraint J11 on sys_clk_pin is invalid: No such site on

   the device. To bypass this error set the environment variable
   'XIL_MAP_LOCWARN'.

  

   J11 is the clock constraint of xc5vl50tff665-1, the ddr2 device is Hynix HY5PS121621BFP-Y5.

0 Kudos
10,470 Views
Registered: ‎08-21-2008

Re: DDR2 ucf

Hello.

Go to the link mentioned below. Its the pin assignment for Virtex 5 FPGAs...

http://www.xilinx.com/support/documentation/user_guides/ug195.pdf

Check for J11 pin. You will see that it is CCLK which is the configuration clock and it is dedicated for configuration(although there may be primitives that may override this which i don't know). 

The clock pins are different from the CCLK one.

These should be used for Clock inputs and not the CCLK.

Check your Pin out once again. 

Best of luck.
--
Unlimited in my Limits.
0 Kudos
Observer enterliu2000
Observer
10,447 Views
Registered: ‎09-23-2009

Re: DDR2 ucf

hi,

  i set the value XIL_MAP_LOCWARN=1,and now i meet some questions as below:

 

Timing Score: 376

WARNING:Par:62 - Your design did not meet timing.  The following are some suggestions to assist you to meet timing in
   your design.

      Review the timing report using Timing Analyzer (In ISE select "Post-Place &
      Route Static Timing Report").  Go to the failing constraint(s) and select
      the "Timing Improvement Wizard" link for suggestions to correct each problem.

   Try the Design Goal and Strategies for Timing Performance (In ISE select Project -> Design Goals & Strategies) to
   ensure the best options are set in the tools for timing closure.

   Use the Xilinx "SmartXplorer" script to try special combinations of
   options known to produce very good results.

INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no
   requested value.
Number of Timing Constraints that were not applied: 1

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------
  Constraint                                |  Check  | Worst Case |  Best Case | Timing |   Timing  
                                            |         |    Slack   | Achievable | Errors |    Score  
------------------------------------------------------------------------------------------------------
* TS_clock_generator_0_clock_generator_0_PL | SETUP   |     0.030ns|     7.970ns|       0|           0
  L0_CLK_OUT_0_ = PERIOD TIMEGRP         "c | HOLD    |    -0.100ns|            |       4|         376
  lock_generator_0_clock_generator_0_PLL0_C |         |            |            |        |           
  LK_OUT_0_" TS_sys_clk_pin /         1.25  |         |            |            |        |           
  HIGH 50%                                  |         |            |            |        |           
------------------------------------------------------------------------------------------------------
  TS_clock_generator_0_clock_generator_0_PL | SETUP   |     0.276ns|    15.448ns|       0|           0
  L0_CLK_OUT_3_ = PERIOD TIMEGRP         "c | HOLD    |     0.186ns|            |       0|           0
  lock_generator_0_clock_generator_0_PLL0_C |         |            |            |        |           
  LK_OUT_3_" TS_sys_clk_pin /         0.625 |         |            |            |        |           
   HIGH 50%                                 |         |            |            |        |           
------------------------------------------------------------------------------------------------------
  TS_clock_generator_0_clock_generator_0_PL | SETUP   |     2.273ns|     4.030ns|       0|           0
  L0_CLK_OUT_1_ = PERIOD TIMEGRP         "c | HOLD    |     0.351ns|            |       0|           0
  lock_generator_0_clock_generator_0_PLL0_C |         |            |            |        |           
  LK_OUT_1_" TS_sys_clk_pin /         1.25  |         |            |            |        |           
  PHASE 2 ns HIGH 50%                       |         |            |            |        |           
------------------------------------------------------------------------------------------------------
  TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | N/A     |         N/A|         N/A|     N/A|         N/A
  pin" 10 ns HIGH 50%                       |         |            |            |        |           
------------------------------------------------------------------------------------------------------


Derived Constraint Report
Derived Constraints for TS_sys_clk_pin
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_sys_clk_pin                 |     10.000ns|          N/A|      9.963ns|            0|            4|            0|       443527|
| TS_clock_generator_0_clock_gen|      8.000ns|      7.970ns|          N/A|            4|            0|       435464|            0|
| erator_0_PLL0_CLK_OUT_0_      |             |             |             |             |             |             |             |
| TS_clock_generator_0_clock_gen|      8.000ns|      4.030ns|          N/A|            0|            0|          459|            0|
| erator_0_PLL0_CLK_OUT_1_      |             |             |             |             |             |             |             |
| TS_clock_generator_0_clock_gen|     16.000ns|     15.448ns|          N/A|            0|            0|         7604|            0|
| erator_0_PLL0_CLK_OUT_3_      |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

1 constraint not met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.


Generating Pad Report.

1 signals are not completely routed.

WARNING:Par:100 - Design is not completely routed.

Loading device for application Rf_Device from file '5vlx50t.nph' in environment d:\Xilinx\10.1\ISE;D:\Xilinx\10.1\EDK.
INFO:ParHelpers:197 - Number of "Exact" mode Directed Routing Constraints: 64
WARNING:ParHelpers:198 - One or more "EXACT" mode Directed Routing constrained net(s) were not successfully routed
   according to the constraint(s). The router attempted to route the net(s) without regard to the constraint. The number
   of nets found with Directed Routing Constraints: 64, number successfully routed using the constraints: 0, number
   failed: 64. The failed nets are listed below. Please use FPGA Editor to determine the cause of the failure.
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[1].u_iob_dq/stg1_out_fall_0s
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[1].u_iob_dq/stg1_out_rise_0s
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[28].u_iob_dq/stg1_out_fall_0s
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[28].u_iob_dq/stg1_out_rise_0s
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[8].u_iob_dq/stg1_out_rise_0m
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[8].u_iob_dq/stg1_out_fall_0m
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[18].u_iob_dq/stg1_out_fall_0s
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[18].u_iob_dq/stg1_out_rise_0s
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[26].u_iob_dq/stg1_out_rise_0m
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[26].u_iob_dq/stg1_out_fall_0m
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[6].u_iob_dq/stg1_out_fall_0s
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[6].u_iob_dq/stg1_out_rise_0s
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[24].u_iob_dq/stg1_out_fall_0s
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[24].u_iob_dq/stg1_out_rise_0s
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[16].u_iob_dq/stg1_out_rise_0m
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[16].u_iob_dq/stg1_out_fall_0m
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[21].u_iob_dq/stg1_out_fall_0s
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[21].u_iob_dq/stg1_out_rise_0s
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[13].u_iob_dq/stg1_out_fall_0s
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[13].u_iob_dq/stg1_out_rise_0s
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[4].u_iob_dq/stg1_out_rise_0m
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[4].u_iob_dq/stg1_out_fall_0m
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[11].u_iob_dq/stg1_out_fall_0s
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[11].u_iob_dq/stg1_out_rise_0s
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[2].u_iob_dq/stg1_out_rise_0m
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[2].u_iob_dq/stg1_out_fall_0m
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[29].u_iob_dq/stg1_out_rise_0m
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[29].u_iob_dq/stg1_out_fall_0m
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[0].u_iob_dq/stg1_out_fall_0s
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[0].u_iob_dq/stg1_out_rise_0s
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mp
mc_phy_if_0/u_phy_io_0/gen_dq[9].u_iob_dq/stg1_out_fall_0s
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[9].u_iob_dq/stg1_out_rise_0s
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[19].u_iob_dq/stg1_out_fall_0s
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[19].u_iob_dq/stg1_out_rise_0s
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[27].u_iob_dq/stg1_out_rise_0m
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[27].u_iob_dq/stg1_out_fall_0m
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[7].u_iob_dq/stg1_out_rise_0m
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[7].u_iob_dq/stg1_out_fall_0m
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[25].u_iob_dq/stg1_out_rise_0m
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[25].u_iob_dq/stg1_out_fall_0m
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[17].u_iob_dq/stg1_out_rise_0m
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[17].u_iob_dq/stg1_out_fall_0m
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[30].u_iob_dq/stg1_out_fall_0s
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[30].u_iob_dq/stg1_out_rise_0s
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[22].u_iob_dq/stg1_out_rise_0m
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[22].u_iob_dq/stg1_out_fall_0m
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[14].u_iob_dq/stg1_out_rise_0m
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[14].u_iob_dq/stg1_out_fall_0m
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[5].u_iob_dq/stg1_out_rise_0m
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[5].u_iob_dq/stg1_out_fall_0m
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[31].u_iob_dq/stg1_out_fall_0s
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[31].u_iob_dq/stg1_out_rise_0s
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[23].u_iob_dq/stg1_out_rise_0m
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[23].u_iob_dq/stg1_out_fall_0m
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[15].u_iob_dq/stg1_out_rise_0m
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[15].u_iob_dq/stg1_out_fall_0m
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[20].u_iob_dq/stg1_out_fall_0s
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[20].u_iob_dq/stg1_out_rise_0s
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[12].u_iob_dq/stg1_out_fall_0s
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[12].u_iob_dq/stg1_out_rise_0s
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[3].u_iob_dq/stg1_out_rise_0m
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[3].u_iob_dq/stg1_out_fall_0m
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[10].u_iob_dq/stg1_out_fall_0s
 Net DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[10].u_iob_dq/stg1_out_rise_0s
Total REAL time to PAR completion: 1 mins 22 secs
Total CPU time to PAR completion: 1 mins 17 secs

Peak Memory Usage:  441 MB

Placer: Placement generated during map.
Routing: Completed - errors found.
Timing: Completed - 4 errors found.

Number of error messages: 0
Number of warning messages: 6
Number of info messages: 3

Writing design to file system.ncd

 

PAR done!
ERROR:Xflow - Program par returned error code 30. Aborting flow execution...
make: *** [__xps/system_routed] Error 1
Done!

I'd like to ask how to solve these problems.

Thank you for your help!

0 Kudos
2,793 Views
Registered: ‎08-21-2008

Re: DDR2 ucf

Hello.

I told you not to use CCLK pin as your input clock pin.

It will result in  timing issues for clock generator to output clk0.

By the way at what frequency you are running your system. 

Best of luck.
--
Unlimited in my Limits.