UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Adventurer
Adventurer
3,598 Views
Registered: ‎07-20-2010

DDR3 clock in SP605 microblaze reference design

Jump to solution

Hi,

I am working with SP605 board with Spartan6. In microblaze reference designs (BIST or stand alone or Xapp1026's design) pair of ddr3 clock generated by clock_generator block is about 600 MHz (one with 0 phase and the other with 180 degree phase). This pair of clocks is input for ddr memory controller. From spartan6 datasheet I read that maximum data rate for DDR3 memory controller of devices of speed grade -3 is 800 Mbit/sec, then maximum clock frequency should be 400 MHz, not over. For example, in the reference design for Spartan6 Microboard, equipped with LPDDR, maximum data rate is 400 Mbit/sec, and the two ddr clocks are 200 MHz correctly.

Am I missing anything?

 

Begos

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Adventurer
Adventurer
4,742 Views
Registered: ‎07-20-2010

Re: DDR3 clock in SP605 microblaze reference design

Jump to solution

Hi,

I was in error, reference design is "almost" correct, execpt for a little thing.

If I have a DDR memory that is working, for example, at 400 Mbit/sec, the clock in output from memory controller must be 200 MHz. Memory controller needs a clock double of its output. For an output clock of 200 MHz it needs an input clock of 400 MHz. In the microboard reference design LPDDR2 is working at 400 Mb/sec with a ddr clock of 200 MHZ. Clock generator is generating a clock of 400 MHz for Spartan 6 memory controller, and this is correct.

 

A clock of 600 MHz in input at the memory controller generates an ouput clock of 300 MHz. But for DDR3 Spartan 6 memory controller need a minimum output clock of 303 MHz, this is reason because reference design seems to be  "almost" correct. In another reference design where input clock is 666 MHz output clock is 333 MHZ, and this is all ok.

 

I apologize for my error.

 

Begos

4 Replies
Xilinx Employee
Xilinx Employee
3,594 Views
Registered: ‎07-11-2011

Re: DDR3 clock in SP605 microblaze reference design

Jump to solution

Hi,

 

MIG/DDR3 Controller max frequency is only 400MHZ, I think Xapp1026  will have design files for ML605(v6) as well, can you confirm if you did see 600MHZ for S6 and not V6?

 

Regards,

Vanitha

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
0 Kudos
Adventurer
Adventurer
3,580 Views
Registered: ‎07-20-2010

Re: DDR3 clock in SP605 microblaze reference design

Jump to solution

Hi,

xapp 1026 has design files for ML605 too, but I can confirm that 600 MHz is in SP605 designs for Spartan6. I have explored edk 14.3 design and 13.1 design.  Frequency too high is not only in Xapp 1026 designs, but in SP605 BIST and SP605 Standalone application (edk 13.4) too, where frequency is 666 MHz! For example I have attached mhs file from ethernet lite 8kb cache from Xapp 1026.

 

Regards,

Begos

0 Kudos
Adventurer
Adventurer
3,537 Views
Registered: ‎07-20-2010

Re: DDR3 clock in SP605 microblaze reference design

Jump to solution

Hi Vanitha,

do you have any news about issue?

Regards,

 

Begos

0 Kudos
Highlighted
Adventurer
Adventurer
4,743 Views
Registered: ‎07-20-2010

Re: DDR3 clock in SP605 microblaze reference design

Jump to solution

Hi,

I was in error, reference design is "almost" correct, execpt for a little thing.

If I have a DDR memory that is working, for example, at 400 Mbit/sec, the clock in output from memory controller must be 200 MHz. Memory controller needs a clock double of its output. For an output clock of 200 MHz it needs an input clock of 400 MHz. In the microboard reference design LPDDR2 is working at 400 Mb/sec with a ddr clock of 200 MHZ. Clock generator is generating a clock of 400 MHz for Spartan 6 memory controller, and this is correct.

 

A clock of 600 MHz in input at the memory controller generates an ouput clock of 300 MHz. But for DDR3 Spartan 6 memory controller need a minimum output clock of 303 MHz, this is reason because reference design seems to be  "almost" correct. In another reference design where input clock is 666 MHz output clock is 333 MHZ, and this is all ok.

 

I apologize for my error.

 

Begos