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golson
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Registered: ‎04-07-2008

DMA Memory location all zeroed out

Hi,

  I am trying to figure out why my dma does not work.  In the process of debug I dumped the memory where I expected the DMA to be assigned to.

 

I assigned the PLB_CENTRAL_DMA to be at address 0x40000000 and I connected the SPLB bus to the mb_plb bus.  Then I started running my program and

created a break point in the middle of the program after some of the DMA commands had been executed.  I dumped the memory at the

0x40000000 range and though this area the memory is reading all zeros.

 

 

Can anyone explain this?

 

Thank You,

  Gary Olson

 

 

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golson
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Registered: ‎04-07-2008

Here is the MHS

 

# ##############################################################################

# Created by Base System Builder Wizard for Xilinx EDK 10.1 Build EDK_K.15

# Fri May 16 10:15:24 2008

# Target Board: Xilinx Virtex 5 ML505 Evaluation Platform Rev 1

# Family: virtex5

# Device: xc5vlx50t

# Package: ff1136

# Speed Grade: -1

# Processor: microblaze_0

# System clock frequency: 125.00 MHz

# On Chip Memory : 16 KB

# Total Off Chip Memory : 257 MB

# - SRAM = 1 MB

# - DDR2_SDRAM = 256 MB

# ##############################################################################

PARAMETER VERSION = 2.1.0

 

PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = I

PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = O

PORT fpga_0_LEDs_8Bit_GPIO_IO_pin = fpga_0_LEDs_8Bit_GPIO_IO, DIR = IO, VEC = [0:7]

PORT fpga_0_SRAM_Mem_A_pin = fpga_0_SRAM_Mem_A, DIR = O, VEC = [7:30]

PORT fpga_0_SRAM_Mem_DQ_pin = fpga_0_SRAM_Mem_DQ, DIR = IO, VEC = [0:31]

PORT fpga_0_SRAM_Mem_BEN_pin = fpga_0_SRAM_Mem_BEN, DIR = O, VEC = [0:3]

PORT fpga_0_SRAM_Mem_OEN_pin = fpga_0_SRAM_Mem_OEN, DIR = O

PORT fpga_0_SRAM_Mem_CEN_pin = fpga_0_SRAM_Mem_CEN, DIR = O

PORT fpga_0_SRAM_Mem_ADV_LDN_pin = fpga_0_SRAM_Mem_ADV_LDN, DIR = O

PORT fpga_0_SRAM_Mem_WEN_pin = fpga_0_SRAM_Mem_WEN, DIR = O

PORT fpga_0_DDR2_SDRAM_DDR2_ODT_pin = fpga_0_DDR2_SDRAM_DDR2_ODT, DIR = O, VEC = [1:0]

PORT fpga_0_DDR2_SDRAM_DDR2_Addr_pin = fpga_0_DDR2_SDRAM_DDR2_Addr, DIR = O, VEC = [12:0]

PORT fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin = fpga_0_DDR2_SDRAM_DDR2_BankAddr, DIR = O, VEC = [1:0]

PORT fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin = fpga_0_DDR2_SDRAM_DDR2_CAS_n, DIR = O

PORT fpga_0_DDR2_SDRAM_DDR2_CE_pin = fpga_0_DDR2_SDRAM_DDR2_CE, DIR = O, VEC = [1:0]

PORT fpga_0_DDR2_SDRAM_DDR2_CS_n_pin = fpga_0_DDR2_SDRAM_DDR2_CS_n, DIR = O, VEC = [1:0]

PORT fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin = fpga_0_DDR2_SDRAM_DDR2_RAS_n, DIR = O

PORT fpga_0_DDR2_SDRAM_DDR2_WE_n_pin = fpga_0_DDR2_SDRAM_DDR2_WE_n, DIR = O

PORT fpga_0_DDR2_SDRAM_DDR2_Clk_pin = fpga_0_DDR2_SDRAM_DDR2_Clk, DIR = O, VEC = [1:0]

PORT fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin = fpga_0_DDR2_SDRAM_DDR2_Clk_n, DIR = O, VEC = [1:0]

PORT fpga_0_DDR2_SDRAM_DDR2_DM_pin = fpga_0_DDR2_SDRAM_DDR2_DM, DIR = O, VEC = [7:0]

PORT fpga_0_DDR2_SDRAM_DDR2_DQS = fpga_0_DDR2_SDRAM_DDR2_DQS, DIR = IO, VEC = [7:0]

PORT fpga_0_DDR2_SDRAM_DDR2_DQS_n = fpga_0_DDR2_SDRAM_DDR2_DQS_n, DIR = IO, VEC = [7:0]

PORT fpga_0_DDR2_SDRAM_DDR2_DQ = fpga_0_DDR2_SDRAM_DDR2_DQ, DIR = IO, VEC = [63:0]

PORT fpga_0_SRAM_CLK = ZBT_CLK_OUT_s, DIR = O

PORT fpga_0_SRAM_CLK_FB = ZBT_CLK_FB_s, DIR = I, SIGIS = CLK, CLK_FREQ = 125000000

PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000

PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST

 

BEGIN microblaze

PARAMETER INSTANCE = microblaze_0

PARAMETER C_INTERCONNECT = 1

PARAMETER HW_VER = 7.10.a

PARAMETER C_DEBUG_ENABLED = 1

BUS_INTERFACE DLMB = dlmb

BUS_INTERFACE ILMB = ilmb

BUS_INTERFACE DPLB = mb_plb

BUS_INTERFACE IPLB = mb_plb

BUS_INTERFACE DEBUG = microblaze_0_dbg

PORT MB_RESET = mb_reset

PORT INTERRUPT = xps_intc_0_Irq

END

BEGIN plb_v46

PARAMETER INSTANCE = mb_plb

PARAMETER HW_VER = 1.02.a

PORT PLB_Clk = sys_clk_s

PORT SYS_Rst = sys_bus_reset

END

BEGIN lmb_v10

PARAMETER INSTANCE = ilmb

PARAMETER HW_VER = 1.00.a

PORT LMB_Clk = sys_clk_s

PORT SYS_Rst = sys_bus_reset

END

BEGIN lmb_v10

PARAMETER INSTANCE = dlmb

PARAMETER HW_VER = 1.00.a

PORT LMB_Clk = sys_clk_s

PORT SYS_Rst = sys_bus_reset

END

BEGIN lmb_bram_if_cntlr

PARAMETER INSTANCE = dlmb_cntlr

PARAMETER HW_VER = 2.10.a

PARAMETER C_BASEADDR = 0x00000000

PARAMETER C_HIGHADDR = 0x00003fff

BUS_INTERFACE SLMB = dlmb

BUS_INTERFACE BRAM_PORT = dlmb_port

END

BEGIN lmb_bram_if_cntlr

PARAMETER INSTANCE = ilmb_cntlr

PARAMETER HW_VER = 2.10.a

PARAMETER C_BASEADDR = 0x00000000

PARAMETER C_HIGHADDR = 0x00003fff

BUS_INTERFACE SLMB = ilmb

BUS_INTERFACE BRAM_PORT = ilmb_port

END

BEGIN bram_block

PARAMETER INSTANCE = lmb_bram

PARAMETER HW_VER = 1.00.a

BUS_INTERFACE PORTA = ilmb_port

BUS_INTERFACE PORTB = dlmb_port

END

BEGIN xps_uartlite

PARAMETER INSTANCE = RS232_Uart_1

PARAMETER HW_VER = 1.00.a

PARAMETER C_BAUDRATE = 9600

PARAMETER C_DATA_BITS = 8

PARAMETER C_ODD_PARITY = 0

PARAMETER C_USE_PARITY = 0

PARAMETER C_SPLB_CLK_FREQ_HZ = 125000000

PARAMETER C_BASEADDR = 0x84000000

PARAMETER C_HIGHADDR = 0x8400ffff

BUS_INTERFACE SPLB = mb_plb

PORT RX = fpga_0_RS232_Uart_1_RX

PORT TX = fpga_0_RS232_Uart_1_TX

END

BEGIN xps_gpio

PARAMETER INSTANCE = LEDs_8Bit

PARAMETER HW_VER = 1.00.a

PARAMETER C_GPIO_WIDTH = 8

PARAMETER C_IS_DUAL = 0

PARAMETER C_IS_BIDIR = 1

PARAMETER C_ALL_INPUTS = 0

PARAMETER C_BASEADDR = 0x81400000

PARAMETER C_HIGHADDR = 0x8140ffff

BUS_INTERFACE SPLB = mb_plb

PORT GPIO_IO = fpga_0_LEDs_8Bit_GPIO_IO

END

BEGIN xps_mch_emc

PARAMETER INSTANCE = SRAM

PARAMETER HW_VER = 1.00.a

PARAMETER C_MCH_PLB_CLK_PERIOD_PS = 8000

PARAMETER C_NUM_BANKS_MEM = 1

PARAMETER C_MAX_MEM_WIDTH = 32

PARAMETER C_MEM0_WIDTH = 32

PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 0

PARAMETER C_SYNCH_MEM_0 = 1

PARAMETER C_TCEDV_PS_MEM_0 = 0

PARAMETER C_TWC_PS_MEM_0 = 0

PARAMETER C_TAVDV_PS_MEM_0 = 0

PARAMETER C_TWP_PS_MEM_0 = 0

PARAMETER C_THZCE_PS_MEM_0 = 0

PARAMETER C_THZOE_PS_MEM_0 = 0

PARAMETER C_TLZWE_PS_MEM_0 = 0

PARAMETER C_MEM0_BASEADDR = 0x8a300000

PARAMETER C_MEM0_HIGHADDR = 0x8a3fffff

BUS_INTERFACE SPLB = mb_plb

PORT Mem_A = fpga_0_SRAM_Mem_A_split

PORT Mem_BEN = fpga_0_SRAM_Mem_BEN

PORT Mem_WEN = fpga_0_SRAM_Mem_WEN

PORT Mem_OEN = fpga_0_SRAM_Mem_OEN

PORT Mem_DQ = fpga_0_SRAM_Mem_DQ

PORT Mem_CEN = fpga_0_SRAM_Mem_CEN

PORT Mem_ADV_LDN = fpga_0_SRAM_Mem_ADV_LDN

END

BEGIN mpmc

PARAMETER INSTANCE = DDR2_SDRAM

PARAMETER HW_VER = 4.00.a

PARAMETER C_NUM_PORTS = 1

PARAMETER C_MEM_PARTNO = mt4htf3264h-53e

PARAMETER C_NUM_IDELAYCTRL = 3

PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y5-IDELAYCTRL_X0Y1-IDELAYCTRL_X0Y0

PARAMETER C_MEM_DQS_IO_COL = 0b00_0000_0000_0000_0000

PARAMETER C_MEM_DQ_IO_MS = 0b00000000_01110101_00111101_00001111_00011110_00101110_11000011_11000001_10111100

PARAMETER C_DDR2_DQSN_ENABLE = 1

PARAMETER C_MEM_CE_WIDTH = 2

PARAMETER C_MEM_CS_N_WIDTH = 2

PARAMETER C_MEM_CLK_WIDTH = 2

PARAMETER C_MEM_ODT_WIDTH = 2

PARAMETER C_MEM_ODT_TYPE = 1

PARAMETER C_PIM0_BASETYPE = 2

PARAMETER C_MPMC_CLK0_PERIOD_PS = 8000

PARAMETER C_MPMC_BASEADDR = 0x90000000

PARAMETER C_MPMC_HIGHADDR = 0x9fffffff

BUS_INTERFACE SPLB0 = mb_plb

PORT DDR2_ODT = fpga_0_DDR2_SDRAM_DDR2_ODT

PORT DDR2_Addr = fpga_0_DDR2_SDRAM_DDR2_Addr

PORT DDR2_BankAddr = fpga_0_DDR2_SDRAM_DDR2_BankAddr

PORT DDR2_CAS_n = fpga_0_DDR2_SDRAM_DDR2_CAS_n

PORT DDR2_CE = fpga_0_DDR2_SDRAM_DDR2_CE

PORT DDR2_CS_n = fpga_0_DDR2_SDRAM_DDR2_CS_n

PORT DDR2_RAS_n = fpga_0_DDR2_SDRAM_DDR2_RAS_n

PORT DDR2_WE_n = fpga_0_DDR2_SDRAM_DDR2_WE_n

PORT DDR2_Clk = fpga_0_DDR2_SDRAM_DDR2_Clk

PORT DDR2_Clk_n = fpga_0_DDR2_SDRAM_DDR2_Clk_n

PORT DDR2_DM = fpga_0_DDR2_SDRAM_DDR2_DM

PORT DDR2_DQS = fpga_0_DDR2_SDRAM_DDR2_DQS

PORT DDR2_DQS_n = fpga_0_DDR2_SDRAM_DDR2_DQS_n

PORT DDR2_DQ = fpga_0_DDR2_SDRAM_DDR2_DQ

PORT MPMC_Clk0 = sys_clk_s

PORT MPMC_Clk90 = DDR2_SDRAM_mpmc_clk_90_s

PORT MPMC_Clk_200MHz = clk_200mhz_s

PORT MPMC_Clk0_DIV2 = DDR2_SDRAM_MPMC_Clk_Div2

PORT MPMC_Rst = sys_periph_reset

END

BEGIN util_bus_split

PARAMETER INSTANCE = SRAM_util_bus_split_2

PARAMETER HW_VER = 1.00.a

PARAMETER C_SIZE_IN = 32

PARAMETER C_LEFT_POS = 7

PARAMETER C_SPLIT = 31

PORT Sig = fpga_0_SRAM_Mem_A_split

PORT Out1 = fpga_0_SRAM_Mem_A

END

BEGIN clock_generator

PARAMETER INSTANCE = clock_generator_0

PARAMETER HW_VER = 2.00.a

PARAMETER C_EXT_RESET_HIGH = 1

PARAMETER C_CLKIN_FREQ = 100000000

PARAMETER C_CLKOUT0_FREQ = 125000000

PARAMETER C_CLKOUT0_BUF = TRUE

PARAMETER C_CLKOUT0_PHASE = 0

PARAMETER C_CLKOUT0_GROUP = PLL0

PARAMETER C_CLKOUT1_FREQ = 125000000

PARAMETER C_CLKOUT1_BUF = TRUE

PARAMETER C_CLKOUT1_PHASE = 90

PARAMETER C_CLKOUT1_GROUP = PLL0

PARAMETER C_CLKOUT2_FREQ = 200000000

PARAMETER C_CLKOUT2_BUF = TRUE

PARAMETER C_CLKOUT2_PHASE = 0

PARAMETER C_CLKOUT2_GROUP = NONE

PARAMETER C_CLKOUT3_FREQ = 62500000

PARAMETER C_CLKOUT3_BUF = TRUE

PARAMETER C_CLKOUT3_PHASE = 0

PARAMETER C_CLKOUT3_GROUP = NONE

PARAMETER C_CLKFBIN_FREQ = 125000000

PARAMETER C_CLKFBOUT_FREQ = 125000000

PARAMETER C_CLKFBOUT_BUF = TRUE

PORT CLKOUT0 = sys_clk_s

PORT CLKOUT1 = DDR2_SDRAM_mpmc_clk_90_s

PORT CLKOUT2 = clk_200mhz_s

PORT CLKOUT3 = DDR2_SDRAM_MPMC_Clk_Div2

PORT CLKIN = dcm_clk_s

PORT LOCKED = Dcm_all_locked

PORT RST = net_gnd

PORT CLKFBIN = ZBT_CLK_FB_s

PORT CLKFBOUT = ZBT_CLK_OUT_s

END

BEGIN mdm

PARAMETER INSTANCE = debug_module

PARAMETER HW_VER = 1.00.b

PARAMETER C_MB_DBG_PORTS = 1

PARAMETER C_USE_UART = 1

PARAMETER C_UART_WIDTH = 8

PARAMETER C_BASEADDR = 0x84400000

PARAMETER C_HIGHADDR = 0x8440ffff

BUS_INTERFACE SPLB = mb_plb

BUS_INTERFACE MBDEBUG_0 = microblaze_0_dbg

PORT Debug_SYS_Rst = Debug_SYS_Rst

END

BEGIN proc_sys_reset

PARAMETER INSTANCE = proc_sys_reset_0

PARAMETER HW_VER = 2.00.a

PARAMETER C_EXT_RESET_HIGH = 0

PORT Slowest_sync_clk = sys_clk_s

PORT Dcm_locked = Dcm_all_locked

PORT Ext_Reset_In = sys_rst_s

PORT MB_Reset = mb_reset

PORT Bus_Struct_Reset = sys_bus_reset

PORT MB_Debug_Sys_Rst = Debug_SYS_Rst

PORT Peripheral_Reset = sys_periph_reset

END

BEGIN xps_central_dma

PARAMETER INSTANCE = xps_central_dma_0

PARAMETER HW_VER = 1.00.a

PARAMETER C_BASEADDR = 0x40000000

PARAMETER C_HIGHADDR = 0x4000FFFF

BUS_INTERFACE SPLB = mb_plb

PORT IP2INTC_Irpt = xps_central_dma_0_IP2INTC_Irpt

END

BEGIN ipif_may18

PARAMETER INSTANCE = ipif_may18_0

PARAMETER HW_VER = 1.01.a

PARAMETER C_BASEADDR = 0x60000000

PARAMETER C_HIGHADDR = 0x6000ffff

BUS_INTERFACE SPLB = mb_plb

PORT IP2INTC_Irpt = ipif_may18_0_IP2INTC_Irpt

END

BEGIN xps_intc

PARAMETER INSTANCE = xps_intc_0

PARAMETER HW_VER = 1.00.a

PARAMETER C_BASEADDR = 0x20000000

PARAMETER C_HIGHADDR = 0x2000ffff

BUS_INTERFACE SPLB = mb_plb

PORT Irq = xps_intc_0_Irq

PORT Intr = xps_central_dma_0_IP2INTC_Irpt&ipif_may18_0_IP2INTC_Irpt

END

 

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golson
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Registered: ‎04-07-2008

I tried hooking DMA component at first to SPLB port.  So now I tried hooking up to MPLB port.  But the Device code does not appear underneath Microblaze_0 libsrc directory.

 

My third attempt is to see what will happen if I hook up the SPLB and MPLB to the mb_plb.

 

This time at least the device code is in the directory.  I also noticed XAPP999 hooked the DMA component that way.  I am in the process of synthesis now.

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golson
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Registered: ‎04-07-2008

Yes, After I hooked up both the SPLB and MPLB ports to the mb_plb.  The DMA seems to be working.
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