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leoc
Visitor
Visitor
3,405 Views
Registered: ‎02-15-2011

DTE and DCE on Spartan 3E and Microblaze Question.

Hello all, hopefully this is in the right for this time, delete this post if it is not.

 

I'd like to start off saying that I am far from being an expert with FPGA development, in fact I am just a beginner. What I do know is that it is possible to use the DCE and DTE ports using ip cores from microblaze on the Spartan 3E. I was wondering what it would take to get them both working at the same time. When I say working, I mean sending and receiving at the same time (not in a concurrent sense).

 

The situation that I am working on without going into too much detail is as follows. I have 3 components, a PC GUI, the FPGA (Spartan 3E) and sensors connected to a microcontroller. The GUI is connected to the FPGA via RS232 cable and the DCE port of the FPGA. The FPGA is connected to the microcontroller via RS232 wireless communication and the DTE port. Now microcontroller is supposed receive serial data sent from the FPGA and it is supposed to send flags to the FPGA based on sensors triggering. These flags are then sent from the FPGA to the GUI and something on the GUI gets triggered. The GUI is also supposed to send data serially (not the flags) to the FPGA and receive those flags from the microcontrollers. So essentially the GUI is supposed to communicate with the microcontroller through the FPGA. Why doesn't the GUI communicate with the microcontroller directly you ask? Another part of the project requires the FPGA to do something unrelated to this because as of right now they are seperate entities. However, to test whether the flags were triggering correctly, I set up the microcontroller and the GUI together (wirelessly) and they work as expected.

 

So right now I believe I am currently sending and receiving using the polling method and the results I am getting is not the same as when I had the GUI and microcontroller communicating together (wirelessly). I think the problem lies with the fact that the transmit and receive buffers are blocked (because the API for the UARTLITE core says so) and are somehow unblocked when I perform the other operation (for example the flag gets sent properly from the uC to the GUI the first time , but it won't get resent until I send data from the GUI to the uC).

 

My question now is should I switch to the interrupt method or will I encounter the same problem? Is there a way to get it working without changing everything? Thanks for keeping up with me this far and I hope to hear some feedback soon.

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3 Replies
austin
Scholar
Scholar
3,402 Views
Registered: ‎02-27-2008

l,

 

What does DTE and DCE have to with any of this?

 

Since the UART is in hardware (luts, dff, wires) in the FPGA, in can do anything you want it to.  If you want to pull two wires highk or low, or different, at once, then you write some RTL (verilog or VHDL) to do it, or you read enough documentation to see if it can be done already in the core.  Given the uBlaze gets clocked at 50 or 100 MHz, worst case you might have to execute more than one instruction to bring both lines to a different state, which is a few tens of nanoseconds.  If that isn't fast enough, then that is one hell of a fast UART serial connection (to be able to relay or respond that fast to the suervisory signals DCE and DTE).

 

If it works wirelessly, what is different?

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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leoc
Visitor
Visitor
3,395 Views
Registered: ‎02-15-2011

You make a good point, I guess I am thinking too much from a microcontroller side and not an FPGA side, even though the FPGA can be a soft-core microcontroller. Do you have any particular documentation with the ipcore itself that you could direct me to? I have been reviewing the examples in the installation directory and I haven't been able to wrap my head around it. Thanks.
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eteam00
Instructor
Instructor
3,379 Views
Registered: ‎07-21-2009

Forgive me if I am mis-interpreting your posts.

 

You seem to be operating under the assumption that you can pick IP (code) blocks off the shelves, connect them together in a design, and your FPGA design work is done.  This may be (somewhat) true for software design, but it is an over-simplification when applied to FPGA design.

 

There is a considerable amount of detail -- which is specifically unique to FPGA design work -- which the FPGA designer must explicitly manage.

 

In the case of a UART core, I would suggest that you look up the core and its documentation, and perhaps even review the core's internal design for insight and understanding.  If it's a Xilinx-supplied core, you can access the design documentation yourself:

  1. Go to website www.xilinx.com
  2. Click on the link in the Products listing for "Intellectual Property"
  3. Search for the core in which you are interested.

-- Bob Elkind

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