07-18-2013 08:06 AM
I have a AXI based core that has two clocks. Clock crossing are taken care of with FIFOs.
I'd like to drive the internal core with 133Mhz, and the video with 100Mhz.
I understand that I need use the "datapathonly" keyword so that only the datapath is analysed but the example in UG216 is not very helpful. Is the following correct?
NET "aclk" PERIOD = 133 Mhz HIGH 50 %;
NET "vid_clk" PERIOD = 100 Mhz HIGH 50 %;
NET "aclk" TNM_NET = "tn_aclk";
NET "vid_clk" TNM_NET = "tn_vid_clk";
#can I use 133 MHz instead of 7.518 ns here?
TIMESPEC "TS_a_to_vid" = FROM "tn_aclk" TO "tn_vid_clk" 7.518 ns DATAPATHONLY;
TIMESPEC "TS_vid_to_a" = FROM "tn_vid_clk" TO "tn_aclk" 10 ns DATAPATHONLY;
In addition I'd like to keep a UCF file with the pcore. I guess it is also possible to keep this within the EDK's UCF, but the design would be more modular if the UCF can be kept with the pcore. Is this possible, and how would I go about doing such a thing.
Thanks in advance for the help.
09-04-2013 01:44 AM
Yes this is right. You could add directly to system.ucf
TIMESPEC "TS_axistreamclks_2_axi4liteclks" = FROM axistream_clk TO axi4lite_clk 20000 ps DATAPATHONLY; #assumes axi4lite_clk <= 50 MHz
TIMESPEC "TS_axi4liteclks_2_axistreamclks" = FROM axi4lite_clk TO axistream_clk 6667 ps DATAPATHONLY; #assumes axistream_clk <= 150 MHz
09-05-2013 05:24 AM
To keep a UCF along with the pcore, you might want to use generate_corelevel_ucf that is available in the most EDK IP's.
Check the snapshot attached for an example.