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cdvervesemi
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Registered: ‎04-28-2018

Debugging BlockRAM based memory used to store AXI stream data

Hi All,

In my design I am generating AXI stream data.

The data goes though DMA to both DDR and BRAM based on FPGA memory. (i.e. after DMA I have a 1 slave 2 master inteconnect to use both memories).

Screenshot 2019-05-08 at 12.32.09 PM.png

When the design is up and running, I can read and write contents of DDR using mrd and mwr commands. This lets me debug the generated data.

How do I debug when using BRAM based memory? The BRAM controller is in 8K address range starting from 0xF0000000. 'mrd' to this address gives "AXI AP transaction error, DAP status 30000021". Currently the BRAM controller is only a slave to AXI DMA configured as only a write channel. Do I need to make a MemoryMap to Stream Read channel to enable reading of this memory? I also tried to make BRAM controller a slave to both DMA and PS, that gives error like this address can not be mapped to zynqmp ps.

Any pointers will be very helpful.

I have already tried doing memmap.

 

Regards

Chinmaya

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stephenm
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Registered: ‎09-12-2007

Add another slave port on your SMC and connect this to the processor interface

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cdvervesemi
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Registered: ‎04-28-2018

Hi @stephenm 

Thanks for the reply.

I tried doing what you said - connecting the BRAM space as a slave to PS.

Auto assign address is not mapping them.

Screenshot 2019-05-10 at 11.46.36 AM.png

I tried adding only the BRAM portion to PS AXI map.

That is also not being mapped.

 

Regards

Chinmaya

 

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stephenm
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Registered: ‎09-12-2007

Can you share a screenshot of your BD please

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cdvervesemi
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Registered: ‎04-28-2018

Screenshot 2019-05-12 at 9.57.14 AM.png

This is the BD.

There is a streaming data flow (which has one HLS block also).

The data need to go to some memory through dma - I have added both ddr and bram as possible data destination.

The question is, when I am using BRAM as destination, how do I check data that got written after dma?

Thanks

Chinmaya

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stephenm
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Registered: ‎09-12-2007

The MRD/MWR command will not use the DMA. If you want to use the DMA to preform a write, then you will need to create an applciation to do this. There is baremetal driver code for the DMA that you can use:

https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/axidma/examples

If you want to use the MRD/MWR command, then you would need to connect as shown below:

bram.PNG

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cdvervesemi
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Registered: ‎04-28-2018

Hi @stephenm 

Thanks for the baremetal axi dma software pointer.

I will go though that and see if that solves my issue.

I had tried the connection you said as in your last reply. Also I understand that theoritically mrd/mwr can not access bram memory if it is a slave only to the dma.

With that connection, somehow the BRAM address space remains unmapped to PS.

I tried adding the PS Master through interconnect, directly to one of the unused AXI master bus on PS. In all cases the BRAM space comes under unmapped slaves.

Regards

Chinmaya

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stephenm
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Registered: ‎09-12-2007

If you do a Auto Assign, does this not add it:

address_space.PNG

 

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cdvervesemi
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Registered: ‎04-28-2018

Hi @stephenm 

I am not trying to use mrd/mwr to send data through DMA.

I have DMA configured as a write channel.

After DMA memory write, I want to have a method to read the memory just to know what got written - for verification/debug.

Regards

Chinmaya

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cdvervesemi
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Registered: ‎04-28-2018

No it does not.

Is it somehow invalid to have this connection in red in your drawing?

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stephenm
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Registered: ‎09-12-2007

Yes, I understand your use case. You can have the DMA access the BRAM and the processor directly. however, you will need to make the connection as shown in my previous thread.

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cdvervesemi
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Registered: ‎04-28-2018

Is it possible that 

-as a slave to DMA, the BRAM 8k space got assigned addr : 0xF000000 to 0xF0001FFF.

-For processor, somehow this address space were already occupied.

So if i manually find 8k address range that processor can use, will it work?

Does address assignment work this way?

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stephenm
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Registered: ‎09-12-2007

Addresses only need to be unique per master

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